Technical Lead Design Verification Engineer

About the role

Astera Labs (NASDAQ: ALAB) is seeking a Technical Lead Design Verification Engineer to join our team. With a focus on complex ASIC verification, this role requires a strong background in electrical engineering, particularly in server, storage, and networking applications. The ideal candidate will have extensive experience in System Verilog, C, C++, Python, or other scripting languages, and will be responsible for the entire verification process, from planning to testing and debugging.

Responsibilities

• Contribute to the functional verification of designs using coding and problem-solving skills.
• Develop and execute test plans in emulation platforms, working closely with software and system validation teams.
• Collaborate with the software and system validation teams to ensure comprehensive test coverage.
• Identify and write coverage measures for various scenarios, ensuring high-quality verification.
• Work independently to develop test plans and sequences, and collaborate with RTL designers to resolve issues.

Requirements

• Strong academic and technical background in electrical engineering, with a minimum of a Bachelor’s degree, and a Master’s degree preferred.
• At least 5 years of experience in verifying and validating complex SoCs for server, storage, and networking applications.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Ability to prioritize and manage multiple tasks effectively, with minimal guidance.
• Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
• Proven ability to use hybrid techniques, including directed and constrained random approaches.
• Experience with different methods of bug detection and coverage hunting, with formal methods experience a plus.
• Ability to work independently to develop test plans and related test sequences, and collaborate with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner cases, ensuring close coverage for high-quality tape-out.

Qualifications

• Authorized to work in the US and able to start immediately.

Benefits

The base salary range for this position is USD 160,000.00 - USD 195,000.00, with the actual salary determined by location, experience, and the pay of employees in similar positions.

Pay

USD 160,000.00 - USD 195,000.00

Schedule

Full-time

Skills

• System Verilog
• C/C++
• Python or other scripting languages
• Experience with System Verilog/UVM
• Experience with directed test methodologies
• Experience with formal methods

Benefits

Health insurance, retirement plan, paid time off, professional development opportunities, and more.