Technical Lead, Design Verification

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell's Photonic Fabric™ team is building next-generation optical interconnect technology for the era of accelerated computing. As AI workloads scale, the bottleneck has shifted from compute to interconnect bandwidth, memory bandwidth, and memory capacity. Our Photonic Fabric delivers a tenfold improvement in performance and energy efficiency deployed as optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB) that integrate into customers' AI accelerators and GPUs. You will play a key role in ensuring our SoCs are functionally correct by defining verification strategies, developing robust UVM environments, and driving continuous improvement of our verification infrastructure.

What You Can Expect

• Experience with protocols such as AMBA (AXI/AHB/APB), PCIe, Ethernet, I2C, SPI, or UART
• Experience with ARM/processor subsystem verification, memory controllers, NoC, or cache designs
• Familiarity with C/C++ for reference modeling or firmware-driven verification
• Familiarity with gate-level simulation and post-silicon validation debug
• Working knowledge of SystemVerilog and UVM methodology, including constrained random verification, coverage-driven techniques, and UVM library development
• Strong scripting skills in Python for verification automation, infrastructure, and tooling
• Experience with industry simulators such as Xcelium, Questa, or VCS
• Strong experience with object-oriented design and implementation
• Excellent communication skills with the ability to collaborate effectively across design, architecture, and software teams

What We're Looking For

• Develop SystemVerilog/UVM verification environments for complex SoCs, from block-level IPs through full-chip integration
• Create detailed verification plans for block, IP, and SoC-level projects, ensuring comprehensive functional and code coverage
• Architect UVM testbenches including stimulus generators, scoreboards, coverage models, and constrained random sequences
• Collaborate closely with design, architecture, and software teams to manage milestones and ensure timely deliverables
• Drive continuous improvement of verification methodologies and processes across the team
• Build and optimize verification infrastructure regression frameworks, coverage tooling, and automation to improve efficiency
• Lead rigorous testbench reviews with designers, architects, and software engineers to uphold verification quality
• Coordinate with software and emulation teams to ensure first-pass tapeout success
• Use leading edge AI tools to develop infrastructure and environments effectively and efficiently

Expected Base Pay Range (USD)

$158,600 - $237,600, $ per annum

Additional Compensation and Benefit Elements

• Employee Stock Purchase Plan with a 2-year look back
• Family support programs to help balance work and home life
• Robust mental health resources to prioritize emotional well-being
• A recognition and service awards to celebrate contributions and milestones

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.