Test Design Hardware Developer
IBM · Poughkeepsie, AR · 2 wk ago
HybridEngineeringFull-time
Role and Responsibilities
- Developing and integrating DFT architectures including scan insertion, boundary scan, MBIST, and JTAG.
- Utilizing Synopsys tools such as DFT Compiler, TetraMax and TestMax for design testability analysis and test point insertion.
- Generating test patterns, simulating fault coverage and validating correct circuit behavior and coverage.
- Supporting silicon bring-up and failure analysis with test vectors and diagnostics.
- Driving DFT methodology improvements and automation for efficiency and scalability.
- Collaborating with cross-functional teams to ensure DFT requirements are met throughout the design cycle.
Education and Technical Expertise
- Master's Degree Required
- 5+ years of hands-on experience in DFT implementation for complex ASIC/SoC designs in advanced process nodes (e.g., 7nm, 5nm, or below).
- Proven expertise with Synopsys DFT tools including DFT Compiler, TetraMAX, TestMAX, and Formality.
- Deep understanding of scan architecture, ATPG, boundary scan, MBIST, IJTAG, and hierarchical DFT methodologies.
- Demonstrated experience in developing and deploying DFT strategies across multiple tape-outs.
- Strong scripting skills in Python, TCL, and Bash for automation and tool integration.
- Solid grasp of IEEE1500, IEEE1687, fault models (stuck-at, transition, path delay, bridging), and test coverage metrics.
- Experience working in Unix/Linux-based environments with large-scale computing and version control systems (e.g., Git).
Preferred Technical and Professional Experience
- 10+ years of experience in DFT with a track record of successful silicon bring-up and production test support.
- Experience with low-power DFT techniques, scan compression, and hierarchical DFT.
- Experience with DFT-aware physical design flows, including timing closure and floorplanning for test logic.
- Proficiency in Makefile-based build systems and CI/CD pipelines for regression and test automation.
- Experience mentoring junior engineers and leading cross-functional DFT initiatives.