Technologist, Hardware Development Engineering

WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide. This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today. We’re looking for people who want to build, solve, and operate at that level. Join us and let’s shape the future of data.

About the role

We are seeking an Expert-level Hardware Engineer who is equally strong in board-level hardware design and ASIC interface/integration (I/O, package, power integrity, DFT/test, analog, and signal integrity). This is a hands-on role for a recognized subject matter expert in delivering complex hardware from concept through production, including deep lab bring-up and root-cause of complex issues, able to debug across silicon, package, and board.

Responsibilities

• Ownership of multiple complex programs through the full lifecycle: architecture → design → build → bring-up → debug → qualification → production ramp → sustaining.
• Board/system hardware design (schematic ownership, layout partnership, bring-up, debug, standards compliance, manufacturing support).
• ASIC I/O and integration (I/O architecture decisions, package/substrate considerations, PI/SI co-design, tape-out support, DFT/test hooks).
• Design and simulate high-speed links across die/ASIC package/PCB/connectors/cabling, balancing SI/PI/EMI and manufacturing constraints.
• Design complex boards using cutting-edge FPGAs, including power architecture, high-speed transceiver channel design, reference clock design, reset/boot/strap, and bring-up/debug using vendor tools.
• Own FPGA-based platform bring-up from first power-on through high-speed link validation and system integration.
• Expert schematic design and review for high-complexity boards (compute/networking/accelerator-class or equivalent), including multi-rail power distribution, high-speed interfaces (DDR, PCIe, Ethernet/SerDes, USB, I2C, SPI, MIPI), controlled impedance trace design, clocking/reset architectures, and analog circuit design.
• Partner with layout teams to define and enforce stackups, reference planes, return paths, via design, routing constraints, differential pair controlled impedance routing, and manufacturability.
• Signal Integrity (SI) and Power Integrity (PI) design across die/package/board, including insertion loss, return loss, eye/jitter concepts, electrical noise abatement, target impedance, decap strategy, anti-resonance mitigation, and EMI/EMC grounding/shielding.
• Own or co-own ASIC I/O choices, including I/O standards, voltage domains, ESD strategy, drive/slew tuning, noise coupling/SSO considerations, and package/substrate impacts (pinout tradeoffs, escape routing, lane swapping, parasitics).
• Define DFT and manufacturing test strategy, including JTAG/boundary scan, scan/ATPG, BIST/loopbacks/PRBS, test access, test point strategy, and failure analysis workflows.
• Own/review analog subsystems relevant to high-performance designs, including clock generation/distribution, filtering/biasing, mixed-signal partitioning, and grounding strategy.
• Lead structured bring-up and root-cause debug, including EVT test plan creation, high-speed measurements (oscilloscopes, BERT, network analyzers), and correlation of bench measurements to simulation.
• Operate as a cross-functional technical leader across silicon, package, board, validation, test, and manufacturing, driving design reviews, mentoring engineers, and writing clear specs/constraints to prevent rework.
• Drive partnerships with key IP, component, and manufacturers.

Qualifications

• Professional hardware engineering experience.
• Hands-on experience integrating and debugging leading-edge Ethernet and PCIe interfaces, including:
  • 100G/200G Ethernet PAM4 transceivers (system/channel design, equalization concepts, BER/PRBS testing, standards compliance).
  • PCIe Gen 6 (system/channel design, equalization concepts, BER/PRBS testing, standards compliance).
• Proven experience designing complex boards using cutting-edge FPGAs (e.g., high-end families with high-speed transceivers).
• Board-level design expertise with multi-rail power distribution, high-speed interfaces (DDR, PCIe, Ethernet/SerDes, USB, I2C, SPI, MIPI), controlled impedance trace design, and clocking/reset architectures.
• Strong Signal Integrity (SI) and Power Integrity (PI) experience across die/package/board, including insertion loss, return loss, eye/jitter, target impedance, decap strategy, and EMI/EMC grounding/shielding.
• ASIC I/O and package co-design experience, including I/O standards, voltage domains, ESD strategy, package parasitics, and power architecture.
• DFT/test strategy experience, including JTAG/boundary scan, scan/ATPG, BIST/loopbacks/PRBS, test access, and failure analysis.
• Practical analog and mixed-signal design capability, including clock generation/distribution, filtering/biasing, and grounding strategy.
• Hands-on lab debug expertise, including high-speed measurements (oscilloscopes, BERT, network analyzers), probing strategy, and correlation to simulation.
• Familiarity with schematic/layout tools (Cadence/Altium/Mentor) and SI/PI modeling workflows (IBIS/AMI, S-parameters, SPICE).
• Examples of personally identifying high-speed margin failures (e.g., 100/200G PAM4, PCIe Gen 6) through SI/PI analysis or lab testing.
• Examples of cross-boundary root cause (ASIC ↔ package ↔ board) with measurable corrective actions.
• Examples of improving observability/DFT/test hooks to accelerate bring-up and production readiness.

Preferred Qualifications

• Advanced packaging or multi-die systems (e.g., chiplets/interposers/HBM-class integration).
• Ownership of qualification/compliance (EMC, safety, thermal/mechanical) and production yield improvement.
• Experience with design for low cost, second-source strategies, and sustained field reliability initiatives.
• AMD FPGA knowledge.

Benefits

• Paid vacation time and sick leave.
• Medical, dental, and vision insurance.
• Life, accident, and disability insurance.
• Tax-advantaged flexible spending and health savings accounts.
• Employee assistance program.
• Voluntary benefit programs (supplemental life, AD&D, legal plan, pet insurance, critical illness, accident, hospital indemnity).
• Tuition reimbursement.
• Transit benefits.
• Applause Program.
• Employee stock purchase plan.
• WD Savings 401(k) Plan.
• Short Term Incentive Plan (STI) or Sales Incentive Plan (SIP) bonuses based on company and individual performance.
• Annual Long-Term Incentive (LTI) program, including restricted stock units (RSUs) or cash equivalents.