Technologist, Hardware Development Engineering

About the Role

We are seeking an Expert-level Hardware Engineer who is equally strong in board-level hardware design and ASIC interface / integration (I/O, package, power integrity, DFT/test, analog, and signal integrity). This is a hands-on role for a recognized subject matter expertise in delivering complex hardware from concept through production, including deep lab bring-up and root-cause complex issues, able to debug across silicon, package, and board.

Responsibilities

• Own or co-own complex programs through the full lifecycle: architecture → design → build → bring-up → debug → qualification → production ramp → sustaining.
• Own schematic design and review for high-complexity boards (compute/networking/accelerator-class or equivalent).
• Partner with layout teams to define and enforce stackups, reference planes, return paths, via design and strategy, routing constraints, differential pair controlled impedance routing, channel constraints, connector strategy, and manufacturability.
• Design and simulate high-speed links across die/ASIC package/PCB/connectors/cabling, balancing SI/PI/EMI and manufacturing constraints.
• Own or co-own ASIC I/O choices including I/O standards, voltage domains, ESD strategy, drive/slew tuning, and noise coupling/SSO considerations.
• Define debug and manufacturing test strategy, including test access, test point strategy, coverage vs SI impact, and failure analysis workflows.
• Own or review analog subsystems relevant to high-performance designs: clock generation/distribution, filtering/biasing, mixed-signal partitioning, and grounding strategy.
• Create and execute EVT test plans; perform structured bring-up and root-cause debug using high-speed measurement equipment (Oscilloscopes, BERT, network analyzers, spectrum analyzers).
• Correlate bench measurements back to simulation and drive corrective actions.
• Write clear specs and constraints that prevent rework (I/O requirements, channel budgets, PDN targets, bring-up/test access).
• Drive design reviews that identify real risks early and mentor engineers across experience levels.
• Drive partnerships with key IP, component, and manufacturers.

Required Qualifications

• Professional hardware engineering experience with proven ownership of multiple complex programs through the full lifecycle.
• Demonstrated hands-on experience spanning both:
  • Board/system hardware design (schematic ownership, layout partnership, bring-up, debug, standards compliance, manufacturing support)
  • ASIC I/O and integration (I/O architecture decisions, package/substrate considerations, PI/SI co-design, tape-out support, DFT/test hooks)
• Hands-on experience integrating and debugging leading-edge Ethernet and PCIe interfaces, including:
  • 100G/200G Ethernet PAM4 transceivers (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
  • PCIe Gen 6 (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
• Proven experience designing complex boards using cutting-edge FPGAs (e.g., high-end families with high-speed transceivers), including:
  • Power architecture and sequencing for FPGA multi-rail systems
  • High-speed transceiver channel design with associated reference clock design, reset/boot/strap
  • Bring-up and debug using vendor tools, link training, PRBS/IBERT-style testing, and lab correlation
  • Ownership of FPGA-based platform bring-up from first power-on through high-speed link validation and system integration
• Expert schematic design and review for high-complexity boards with strong experience in:
  • Multi-rail power distribution networks (frequency domain impedance control, sequencing, fault handling)
  • High-speed interfaces (DDR, PCIe, Ethernet/SerDes-based links, USB, I2C, SPI, MIPI)
  • Controlled impedance trace design (understanding manufacturing and cost tradeoffs)
  • Clocking/reset/fault tolerant architectures and debug access design
  • General analog circuit design
• Signal Integrity (SI) design experience: insertion loss, return loss, eye/jitter concepts, electrical noise abatement, termination, discontinuities, correlation of models to measurements.
• Deep PI/PDN experience: target impedance approach, decap strategy, anti-resonance mitigation, transient response, measurement and correlation.
• Practical EMI/EMC grounding/shielding/filtering understanding grounded in design and lab realities.
• Strong understanding of package/substrate impacts: pinout/ballout tradeoffs, escape routing constraints, lane swapping realities, package parasitics effects on SI/PI and timing margins, thermal/mechanical considerations influencing reliability and assembly.
• Power architecture competence spanning system and ASIC-aware constraints (noise isolation, domain partitioning, bring-up hooks).
• Strong working knowledge of DFT concepts and productization: JTAG/boundary scan, scan/ATPG fundamentals, BIST/loopbacks/PRBS, on-chip monitors/telemetry.
• Practical capability to own/review analog subsystems: clock generation/distribution and jitter sensitivity, filtering/biasing, stability fundamentals, measurement integrity/noise coupling, mixed-signal partitioning and grounding strategy.
• Expert in structured bring-up and root-cause debug with high-speed measurement competence (Oscilloscopes, BERT, network analyzers, spectrum analyzers, probing strategy, fixtures, de-embedding awareness).
• Familiarity with mainstream schematic/layout environments (e.g., Cadence/Altium/Mentor-class tools) and constraint-driven design practices.
• Comfortable with SI/PI modeling workflows (IBIS/AMI, S-parameters, SPICE-level reasoning) and validation against lab data.
• Strong documentation, design review, ECO, and risk-management discipline.
• Operates as a cross-functional technical leader across silicon, package, board, validation, test, manufacturing.

Preferred Qualifications

• AMD FPGA Knowledge
• Advanced packaging or multi-die systems (e.g., chiplets/interposers/HBM-class integration)
• Ownership of qualification/compliance (EMC, safety, thermal/mechanical) and production yield improvement
• Experience with design for low cost, second-source strategies, and sustained field reliability initiatives

Pay & Benefits

Salary Range: 170,600.00 - 227,400.00

Benefits include paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs. This role is eligible for bonuses under WD's Short Term Incentive Plan or Sales Incentive Plan, and may be eligible to participate in the annual Long-Term Incentive program which consists of restricted stock units or cash equivalents. RSU awards are also available to eligible new hires.