Staff/Senior Staff Physical Design Floorplan & PDN Lead

About the role

We are seeking a high-caliber Staff or Senior Staff Physical Design Engineer with specialized expertise in Floorplanning and Power Delivery Network (PDN) design. This role serves as the architectural bridge between RTL/Systems and the final GDSII, requiring a visionary who understands how floorplan decisions impact the entire PPA (Power, Performance, Area) spectrum. As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity.

Responsibilities

• Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs.
• Strategic PDN Design: Architect and implement complex Power Delivery Networks, defining metal stack usage and grid density to support high-performance cores while minimizing routing congestion.
• EMIR Mastery: Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis, diagnose root causes, and propose architectural or physical fixes without compromising timing.
• Cross-Functional PPA Trade-offs: Collaborate directly with RTL and Architecture teams using "Design Thinking" to influence micro-architecture, suggesting changes to bus widths, pipeline stages, or memory configurations to optimize physical outcomes.
• Methodology Development: Establish best practices and automated flows for floorplanning and PDN synthesis to be used by the wider implementation team.

Requirements

• 10+ years in Physical Design with a proven track record of multiple successful tape-outs at advanced nodes (7nm, 5nm, or 3nm).
• PDN Expertise: Ability to model complex power-up sequences and multi-voltage domains.
• Floorplanning Savvy: Deep proficiency in hierarchical physical design and top-level integration using industry-standard tools (Innovus or IC Compiler II).
• Analysis Skills: Strong understanding of thermal-aware PDN and the physical implications of high-current density paths.
• Scripting: Advanced proficiency in Tcl, Python, or Perl to automate complex floorplanning tasks and data analysis.

Skills

• Critical Thinker: Ability to question constraints and identify "hidden" PPA gains.
• Design Thinking: Empathy for challenges faced by upstream (RTL) and downstream (Sign-off) teams to create holistic solutions.
• Influence: Ability to articulate technical trade-offs to stakeholders.

Qualifications

B.Tech/M.Tech in Electrical/Electronic Engineering or equivalent.

Location: Bangalore (on-site with 2 days remote work option). Department: RTL-to-GDSII / Physical Implementation.