Staff GenAI Engineer - Early PDN Modeling

About the role

We are building the next generation of memory design by embedding AI into how circuits are designed, validated, and brought to silicon. This role is critical to transforming memory design workflows using AI and automation. You will partner closely with design, layout, CAD, and product teams to reduce manual effort, improve quality, and accelerate time-to-tapeout across memory products.

Responsibilities

• Embed AI and automation into PDN analysis, power integrity validation, and optimization workflows
• Apply data-driven methods to predict IR drop, voltage droop, current density, decoupling effectiveness, and electromigration risk during early design stages
• Enable AI-assisted optimization of power grid architectures, bump planning, package-PDN co-design, and decap placement
• Leverage historical design, simulation, and silicon data to drive predictive power integrity insights and design recommendations
• Develop machine learning and generative AI solutions to automate root-cause analysis and accelerate PDN design-space exploration
• Collaborate across power integrity, design, CAD, package, and product engineering teams to scale AI-enabled methodologies and workflows

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience
• 5 to 7 years of experience in power integrity, PDN design, circuit design, physical design, package design, or EDA workflows
• Strong coding skills with the ability to develop and maintain production-quality software in Python or similar languages
• Experience applying data analysis, machine learning, or automation to engineering workflows
• Understanding of power delivery networks, IR drop analysis, voltage integrity, or related semiconductor design domains

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Science, or related field
• Experience applying AI or ML to power integrity, physical design, package design, simulation, or silicon data analysis
• Knowledge of memory subsystem power delivery, package-PDN interactions, and full-chip power integrity methodologies
• Experience with EDA tools and flows for power integrity analysis and optimization
• Familiarity with machine learning techniques such as graph neural networks, surrogate modeling, large language models, or agentic AI systems
• Experience collaborating across design, CAD, package, process integration, test, or product engineering teams

Pay

The US base salary range for this full-time position is $170,000 - $290,000 a year. Additional compensation may include benefits, bonuses, and equity. Salary ranges are determined by role, level, and location, with individual pay based on work location and job-related factors such as knowledge, skills, experience, tenure, and education or training.

Benefits

• A choice of medical, dental, and vision plans
• Income protection programs if unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program and paid holidays