Staff Engineer, Static Timing Analysis CAD Engineer

Position Summary

Samsung, a world leader in advanced semiconductor technology, is seeking a Staff Static Timing Analysis (STA) CAD Engineer to join the Advanced Design Technology and Design Implementation teams at Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL). This role involves ensuring timing integrity and signoff readiness for Samsung's next-generation GPU IPs used in premium smartphones and adjacent market segments.

Role And Responsibilities

• Work closely with design execution teams to ensure effective and efficient flows for complex advanced node designs.
• Innovate and develop cutting-edge solutions for upcoming projects, collaborating with design and EDA partners.
• Develop and implement automation and methodologies for timing analysis to ensure convergent strategies for complex advanced node designs.
• Provide creative solutions utilizing software and hardware expertise to support the needs of STA design teams with complex timing environments.
• Support STA teams by providing automation that simplifies execution, reduces mistakes, and maximizes user efficiency.
• Contribute to technical excellence by applying and helping influence STA methodologies and sign-off flows, leveraging industry-standard tools and exploring best practices.
• Take initiatives on moderate-to-complex projects, communicate openly, document analysis and results, demonstrate strong ownership, and continuously learn by staying ahead of emerging technologies.
• Utilize AI in your work and apply it to improve efficiency with daily engineering tasks.

Skills And Qualifications

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years with a Master’s Degree, or 2+ years with a Ph.D.
• Strong understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals.
• Working knowledge and experience with LLE, POCV, derating methodologies, and timing analysis.
• Strong hands-on experience with industry-standard STA tools (e.g. PrimeTime, StarRC, PrimeClosure, Tempus).
• Strong hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs.
• Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
• Strong scripting /programming skills in Tcl, Python, Perl, Shell script.
• Strong analytical skills, attention to detail, and problem-solving skills using a data-driven approach.
• Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
• Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global team environment.

Total Rewards

• Base pay range: $151,000 - $226,600
• Benefits: Medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and more.
• MBO bonus compensation, long-term incentive plan, and relocation eligibility.
• This is an exempt position, not eligible for overtime pay under the Fair Labor Standards Act (FLSA).