Sr. Staff Engineer, ASIC Design
Ayar Labs · San Jose, CA · 6 days ago
Engineering$180k–$223k/yrFull-time
Key Responsibilities
- Develop detailed digital algorithm specifications in collaboration with analog, photonics, and firmware engineers
- Develop and optimize RTL in verilog for use in complex electro-optical ASICs
- Create models and testbenches for digital and mixed-signal blocks
- Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability)
- Collaborate to ensure timing signoff
- Bringup, evaluation, and debug of in-house custom silicon using python scripting, firmware, and control systems
- Contribute to automated design methodologies and flows for ASIC digital design
- Hands-on work with high-speed interconnects and optical systems
Required Qualifications
- BS in Electrical Engineering, Computer Engineering, or related fields with 5+ years of work or academic experience in ASIC design
- History of assuming responsibility for a variety of technical tasks and completing projects independently
- Mastery of Verilog and SystemVerilog for both RTL design and verification
- Proficient in ASIC verification (XCelium, VCS, Questa) tools
- Proficient in low-level programming languages (C, C++)
- Proficient in Python
- Working knowledge of digital timing constraints and ASIC tool flows
- Experience working on digital designs with multiple clock domains and clock dividers
- Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB)
Preferred Qualifications
- MS in Electrical Engineering, Computer Engineering, or related fields
- Proficient in ASIC synthesis (Genus, Design Compiler) tools
- Proficient in writing timing constraints and deep understanding of timing analysis
- Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
- Performed silicon bring-up, debug, and evaluation
- Working knowledge of FPGAs and/or microcontroller platforms
- Working knowledge of the Cadence Virtuoso design environment, schematic entry, layout, and simulation
- Knowledge of high-speed SerDes or SerDes components
- Some knowledge of optics and control systems
Salary Range
$180,000 - $223,000