Sr Staff Design Verification

Responsibilities

• Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate.
• Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows.
• Create reusable and scalable test bench components that enable efficient and effective verification.
• Closely work on block level and full chip design verification.
• Integrate analog design IPs from vendors and internal teams and develop verification environments for simulation and emulation.
• Work with analog design engineers to create behavioral models for analog designs and with digital design engineers to integrate models/testcase/checkers into upper levels.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 8+ years of design verification and SystemVerilog experience.
• Minimum of 2 years of experience in Python.
• Expertise in developing with the UVM library.
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS.
• Strong problem solver and collaborator.

Preferred Qualifications

• Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6+ years of relevant experience.
• Experience with post-silicon validation and debug.
• Experience with AMS verification.