Sr Staff Application Engineer - Design Verification

We Are:

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are:

• You have spent years in the verification trenches, debugging stubborn mismatches and building flows that actually hold up when the design scales.
• The difference between a verification environment that catches bugs and one that creates them is something you feel in your bones, and you have learned to spot the weak points before they become customer escalations.
• You are equally comfortable sitting with an R&D team discussing simulator architecture and walking a customer through a UVM testbench issue that is blocking their tapeout.
• When a customer says "it worked yesterday," you do not panic. You ask three clarifying questions, pull logs, and usually find the answer in the delta between tool versions or an edge case no one thought to test.
• You think in terms of deployment success, not just feature lists. A tool is only as good as the customer's ability to use it, and you take ownership of that entire arc.
• You do not wait for perfect documentation. You read code, you experiment, you build proof of concepts, and you bring solutions that work.

What You'll Be Doing:

• Lead VCS simulation deployments at customer sites, working directly with design and verification teams to integrate the tool into their existing flows and resolve adoption blockers.
• Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure.
• Partner with field application engineers and R&D to translate customer pain points into actionable product requirements and validate fixes in real customer environments.
• Drive competitive evaluations and benchmarking engagements, demonstrating VCS capabilities against rival simulators and building the technical case for adoption.
• Interface with product validation and R&D teams to propose improvements in simulation accuracy, performance, and usability based on field feedback.
• Support customers using advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows.

The Impact You Will Have:

• Directly enable customer tapeouts by resolving critical verification blockers that would otherwise delay silicon schedules by weeks or months.
• Shape the VCS product roadmap by surfacing real-world deployment challenges and competitive gaps that R&D would not see from internal testing alone.
• Accelerate verification cycles for customers by introducing AI-driven productivity features, advanced debugging techniques, and optimized simulation configurations.
• Win head-to-head benchmarks and convert evaluations into long-term deployments to strengthen Synopsys' competitive position in the simulation market.
• Improve product quality and robustness by identifying edge cases, usability issues, and integration gaps during customer engagements.
• Build deep technical relationships with leading semiconductor companies, becoming the trusted advisor they call when verification gets hard.
• Ensure verification infrastructure does not become the bottleneck for chips powering AI, automotive, mobile, and data center applications.

What You'll Need:

• Bachelor's in Electronics or Computer Engineering with 7+ years of experience, or Master's with 5+ years, focused on digital design verification.
• Deep hands-on experience with simulation technologies, including VCS or equivalent commercial simulators, and strong understanding of event-driven simulation internals.
• Proficiency in SystemVerilog, UVM, SVA, and HDL languages like Verilog and VHDL, with the ability to read and debug complex testbenches and RTL.
• Proven track record debugging simulation mismatches, performance issues, and verification flow problems in production customer environments.
• Strong scripting skills in Perl, TCL, Shell, and Make, with the ability to automate workflows and build tooling that improves engineer productivity.
• Working knowledge of UNIX/Linux environments, version control systems, and large-scale verification infrastructure.
• Experience with Synopsys tools like Verdi, SpyGlass, VC SpyGlass, or exposure to low-power simulation, gate-level verification, and functional safety methodologies is a strong plus.

Who You Are:

• You can walk into a customer war room, quickly assess a broken verification flow, and explain the root cause and fix in terms that make sense to both the engineer debugging it and the manager who needs to know when the schedule recovers.
• Comfortable working across time zones with global R&D teams in India, Europe, and the U.S., balancing multiple customer escalations without losing track of the details that matter.
• You do not need to be the loudest person in the room, but you have a point of view and you push back when a proposed solution does not match the actual problem.
• Organized enough to manage five customer deployments, two competitive evaluations, and an R&D collaboration without dropping threads or missing follow-ups.
• You are genuinely curious about how things work under the hood, whether that is a simulator's scheduling algorithm or a customer's custom verification methodology, and that curiosity makes you better at solving problems.