Sr Staff Design Verification

About the role

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team, collaborating with digital design experts, photonic and analog designers, and the Architecture team to rigorously verify designs using UVM testbench techniques, Real Number Modeling (RNM), and AMS verification methods. This role offers a unique platform to enhance your skills across UVM, AMS modeling, mixed-signal verification, post-silicon validation, formal verification, emulation, and performance modeling and verification. We are hiring at multiple levels.

Responsibilities

• Define and enhance the DV methodologies required for integrated digital, analog, and photonic devices with a strong emphasis on emulation for design verification.
• Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate.
• Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows.
• Create reusable and scalable test bench components that enable efficient and effective verification.
• Close coverage and finish all DV signoff requirements, with a focus on leveraging mixed signal simulations to achieve high coverage metrics.
• Work on block level and full chip design verification.
• Integrate analog design IPs from vendors and internal teams and develop verification environments for simulation and emulation.
• Work with analog design engineers to create behavioral models for analog designs and with digital design engineers to integrate models/testcase/checkers into upper levels.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience.
• Minimum of 8 years of design verification and SystemVerilog experience.
• 2+ years of experience in Python.
• Expertise in developing with the UVM library.
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS.
• Strong problem solver and collaborator.

Preferred Qualifications

• Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6 years of relevant experience.
• Experience with post-silicon validation and debug.
• Experience with AMS verification.

Pay

The base salary range for this role is $224,000 USD - $257,000 USD, determined based on location, experience, educational background, and market data. Total compensation goes beyond base salary and includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution.

Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision).
• Retirement Savings Matching Program.
• Life Insurance (Basic, Voluntary & AD&D).
• Generous Time Off (Vacation, Sick & Public Holidays).
• Paid Family Leave.
• Short Term & Long Term Disability.
• Training & Development.
• Commuter Benefits.
• Flexible, hybrid workplace model.
• Equity grants (applicable to full-time employees).

Benefits eligibility may vary depending on your employment status and location.