Sr Principal ASIC Design Engineer - Terawave

About the role

Blue Origin is seeking ASIC/SOC Design engineers (levels including Principal, Senior Principal) to join our team. These engineers are crucial to ensuring our RFIC/ASIC designs result in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Responsibilities

• Drive end-to-end design and verification methodologies, from writing requirements and specifications to post-silicon bring-up.
• Optimize performance while keeping power low.
• Support back-end teams during DFT, LEC, floorplan, STA.
• Post-Silicon: Post silicon bring up FPGA ASIC to/from FPGA flow.

Requirements

• BS, MS in Electrical Engineering or a related technical discipline.
• 15+ years of experience.
• Deep working knowledge and hands-on experience in innovative verification flows.

Qualifications

• Strong expertise in Verilog/System Verilog, DSP structures, modem SOCs, ARM CPU integration, and interface protocols.
• Experience with clock gating (dynamic and static), multi-voltage SOC front end design, formal verification, functional coverage, module verification, complex subsystem verification, complex SoC verification, co-simulation with software, integration of software build tool flow with simulation, gate simulation, external IP integration, AXI bus, complex high performance DMA, DDR, PCIE, Ethernet, SPI integration, high speed serdes integration, DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface), modem using state of the art DSP, coding, framing (phy and MAC), sequenced and time bound data movement in DSP structures (time slots, time stamps etc), SOC top level integration using models for analog macros, verification using golden reference models in Matlab, SystemC or C, code coverage, timing constraints, support back-end teams during DFT, LEC, floorplan, STA.

Skills

• Verilog/System Verilog experience in designing complex SOCs.
• CDC, RDC, LINT.
• Optimization of performance while keeping power low.
• Experience with clock gating (dynamic and static).
• Front end design for multi-voltage SOCs.
• Formal verification techniques.
• Module and subsystem verification.
• Complex SoC verification.
• Co-simulation with software.
• Integration of software build tool flow with simulation.
• Gate simulation.
• External IP integration.
• ARM CPU single and multi-core integration with bus fabric, GIC, cache, MMU, secure boot.
• AXI bus complex.
• DDR, PCIE, Ethernet, SPI integration.
• High speed serdes integration.
• DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface).
• Modem using state of the art DSP, coding, framing (phy and MAC).
• Sequenced and time bound data movement in DSP structures (time slots, time stamps etc).
• SOC top level integration using models for analog macros.
• Verification using golden reference models in Matlab, SystemC or C.
• Code coverage, timing constraints.
• Support back-end teams during DFT, LEC, floorplan, STA.

Benefits

• Medical, dental, vision, basic and supplemental life insurance.
• Paid parental leave.
• Short and long-term disability.
• 401(k) with a company match of up to 5%.
• Education Support Program.
• Stock options for all regular employees (working at least 20 hours/week).
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

Pay

Base Pay Range For CA applicants is $308,051.00 - $431,270.70 WA applicants is $308,051.00 - $431,270.70 Other Site Ranges May Differ

Schedule

This role is based on site in San Diego, CA; Bay Area, CA; Austin, TX; Kent, WA.