Senior ASIC Design Engineer - Terawave

About the role

Blue Origin is seeking ASIC/SOC Design Validation Engineers (all levels including Senior, Principal, Senior Principal) to join the Design Validation team. This role is based in San Diego, CA; Bay Area, CA; Austin, TX; Kent, WA.

Responsibilities

• Drive verification methodologies, manage test planning and coverage closure
• Ensure seamless portability across multiple verification environments including emulation, FPGA, and silicon bring-up
• Strong expertise in System Verilog, DSP structures, modem SOCs, and interface protocols
• Experience with complex IPs and software co-simulation across all platforms
• Pre-Silicon System Verilog experience in verifying complex SOCs
• Formal verification, functional coverage, definition and collection, module verification, complex subsystem verification, complex SoC verification, co-simulation with software, integration of software build tool flow with simulation, test planning and tracking, coverage closure, methodology and flow, definition and implementation, power estimation, gate simulation, performance analysis, external IP integration, AXI bus, complex high performance NOC and DMADDR, PCIE, Ethernet, SPI, High speed SERDES, DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface), modern modem SOCs using innovative DSP, coding, framing (phy and MAC), sequenced and time bound data movement in DSP structures (time slots, time stamps etc.), AMS verification, SOC top level verification using models for analog macros, verification using golden reference models in MATLAB, SystemC or C, Code coverage, Emulators: qualification for release, compatibility of test cases, reproduce and debug failures, how to partition verification and assess coverage between this and simulation, portable verification across block level and top level, FPGA and ASIC, RTL and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently
• Post-Silicon Post silicon bring up, support for post-silicon and FPGA in the same pre-silicon environment (portable bench/sim platforms), compatibility of test cases, reproduce and debug failures, accelerate software development, FPGA ASIC to/from FPGA flow, Prototyping: qualification for release, different design configurations and top levels, compatibility of test cases, reproduce and debug failures, accelerate software development, how to partition verification and assess coverage between this and simulation, Portable verification across block level and top level, FPGA and ASIC, RTL and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently

Requirements

• BS, MS in Electrical Engineering or a related technical field
• 8+ years of experience
• Deep working knowledge and hands-on experience in innovative verification flows

Qualifications

• Strong expertise in System Verilog, DSP structures, modem SOCs, and interface protocols
• Experience with complex IPs and software co-simulation across all platforms
• Pre-Silicon System Verilog experience in verifying complex SOCs
• Formal verification, functional coverage, definition and collection, module verification, complex subsystem verification, complex SoC verification, co-simulation with software, integration of software build tool flow with simulation, test planning and tracking, coverage closure, methodology and flow, definition and implementation, power estimation, gate simulation, performance analysis, external IP integration, AXI bus, complex high performance NOC and DMADDR, PCIE, Ethernet, SPI, High speed SERDES, DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface), modern modem SOCs using innovative DSP, coding, framing (phy and MAC), sequenced and time bound data movement in DSP structures (time slots, time stamps etc.), AMS verification, SOC top level verification using models for analog macros, verification using golden reference models in MATLAB, SystemC or C, Code coverage, Emulators: qualification for release, compatibility of test cases, reproduce and debug failures, how to partition verification and assess coverage between this and simulation, portable verification across block level and top level, FPGA and ASIC, RTL and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently
• Post-Silicon Post silicon bring up, support for post-silicon and FPGA in the same pre-silicon environment (portable bench/sim platforms), compatibility of test cases, reproduce and debug failures, accelerate software development, FPGA ASIC to/from FPGA flow, Prototyping: qualification for release, different design configurations and top levels, compatibility of test cases, reproduce and debug failures, accelerate software development, how to partition verification and assess coverage between this and simulation, Portable verification across block level and top level, FPGA and ASIC, RTL and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently

Skills

• System Verilog
• DSP structures
• Modem SOCs
• Interface protocols
• Verification methodologies
• Test planning and coverage closure
• Verification environments (emulation, FPGA, silicon)
• Complex IPs and software co-simulation
• Pre-Silicon System Verilog experience
• Formal verification
• Functional coverage, definition and collection
• Module verification
• Complex subsystem verification
• Complex SoC verification
• Co-simulation with software
• Integration of software build tool flow with simulation
• Power estimation
• Gate simulation
• Performance analysis
• External IP integration
• AXI bus
• Complex high performance NOC and DMADDR, PCIE, Ethernet, SPI
• High speed SERDES
• DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface)
• Modern modem SOCs using innovative DSP, coding, framing (phy and MAC)
• Sequenced and time bound data movement in DSP structures (time slots, time stamps etc.)
• AMS verification
• SOC top level verification using models for analog macros
• Verification using golden reference models in MATLAB, SystemC or C
• Code coverage
• Emulators: qualification for release, compatibility of test cases, reproduce and debug failures, how to partition verification and assess coverage between this and simulation, portable verification across block level and top level, FPGA and ASIC, RTL and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently
• Post-Silicon Post silicon bring up, support for post-silicon and FPGA in the same pre-silicon environment (portable bench/sim platforms), compatibility of test cases, reproduce and debug failures, accelerate software development, FPGA ASIC to/from FPGA flow, Prototyping: qualification for release, different design configurations and top levels, compatibility of test cases, reproduce and debug failures, accelerate software development, how to partition verification and assess coverage between this and simulation, Portable verification across block level and top level, FPGA and ASIC, RTL and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently

Benefits

• Medical
• Dental
• Vision
• Basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with a company match of up to 5%
• Education Support Program
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays

Pay

Base Pay Range For CA applicants is $230,398.00 - $322,556.85 WA applicants is $230,398.00 - $322,556.85 Other Site Ranges May Differ

Schedule

Full-time