Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

About the role

AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

We are seeking an experienced Sr. Physical Design STA Engineer to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; we’re handling massive scale and rapid integration of emergent technologies. As a member of the Cloud-Scale Machine Learning Acceleration team, you’ll be responsible for the design and optimization of hardware in our data centers, including technologies such as AWS Inferentia, a machine learning inference product designed to deliver high performance at low cost. You’ll provide leadership in the application of new technologies to large-scale deployments in a continuous effort to deliver a world-class customer experience.

This is a fast-paced, intellectually challenging position, and you’ll work with thought-leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality, and cost.

Responsibilities

• Develop and maintain flows for block and full-chip level static timing analysis.
• Write, debug, and validate timing constraints for blocks and full-chip.
• Run Static Timing Analysis and provide frequent feedback to team members and leads.
• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).
• Develop scripts to automate running timing analysis and generate reports.
• Collaborate with physical design engineers as well as RTL/Architecture teams.

Requirements

• 7+ years of ASIC implementation, synthesis, STA, and physical design in deep sub-micron nodes (16nm or smaller).
• 7+ years of digital design in communication systems.
• 7+ years of full-custom analog or RF layout.
• 7+ years of wireless communications systems and implementation.
• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow.
• 7+ years of verification in communication systems.
• 5+ years of UVM, C, System C, and scripting experience.
• 3+ years of emulation experience.
• Bachelor's degree in Electrical Engineering or a related field.
• Knowledge of UVM and Matlab.
• Knowledge of implementing chips with multiple power islands and power gating.
• Knowledge of multiple access systems including OFDMA, TDMA, and CDMA.
• Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints.
• Knowledge of serial protocols including SPI, I2C, I3C, and UART.
• Knowledge of Python and Embedded C programming.
• Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems, or RF engineering.
• Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2/DVB-C, or related broadband wireless standards.
• Experience leading or solely developing methodology and scripts for physical synthesis.
• Experience taping out chips that have gone into high volume production.
• Experience developing products for volume production.
• Experience with low power design techniques.
• Experience delivering products to volume production.
• Experience in modem L1/L2 algorithms development and architectures.
• Experience in developing link and system level simulators using MATLAB, Python, or C++.
• Experience in test setup automation using MATLAB, Python, or Perl.
• Experience with Agile, TDD, BDD, CI, and Git.
• Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors.
• Experience leading technical initiatives and key deliverables.
• Experience with version control systems and CI/CD pipeline implementation.
• Experience in Bare Metal Environment development, including linker scripts, page tables, and NVIC.
• BS + 8 years, MS + 6 years, or PhD + 4 years in EE/CS.
• Expertise in timing analysis fundamentals.
• 3+ years doing Static Timing Analysis.
• 3+ years with timing constraint development.
• Timing Analysis using EDA tools (e.g., PrimeTime, Tempus, or others).
• Understanding of ASIC Physical Design from RTL-to-GDSII.
• Understanding of other sign-off activities (IR/EM, physical verification, DFT).

Preferred Qualifications

• Master's degree or Ph.D. in Electrical Engineering or related field.
• Experience in RTL coding and debug, as well as performance, power, area analysis, and trade-offs.
• Experience with modern ASIC/FPGA design and verification tools.
• Experience with SOC bring-up and post-silicon validation.
• Expertise developing flows using STA tools (e.g., PrimeTime, Tempus, or others).
• Expertise in ECO flows (e.g., PT-DMSA, Tempus-ECO, Tweaker, or others).
• Experience in advanced nodes - 16nm or below.
• Expertise in parasitic extraction tools (e.g., STAR-RC, Quantus, or others).
• Expertise in circuit-level analysis using tools like SPICE/SPECTRE.
• Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die, etc.

Benefits

• Health insurance (medical, dental, vision, prescription, Basic Life & AD&D, and optional supplemental life plans).
• Employee Assistance Program (EAP) and Mental Health Support.
• Medical Advice Line and Flexible Spending Accounts.
• Adoption and Surrogacy Reimbursement coverage.
• 401(k) matching.
• Paid time off and parental leave.

Pay

USA, CA, Cupertino - $239,600.00 - $324,100.00 USD annually. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on experience, qualifications, and location.

About the team

Utility Computing (UC) AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

Inclusive Team Culture

Here at AWS, it’s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.

Work/Life Balance

We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there’s nothing we can’t achieve in the cloud.