Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

As a member of the Cloud-Scale Machine Learning Acceleration team, you’ll be responsible for the design and optimization of hardware in our data centers, including technologies such as AWS Inferentia—a machine learning inference product designed to deliver high performance at low cost. You’ll provide leadership in the application of new technologies to large-scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought-leaders in multiple technology areas.

Responsibilities

• Develop and maintain flows for block and full-chip level static timing analysis.
• Write, debug, and validate timing constraints for blocks and full-chip.
• Run Static Timing Analysis and provide frequent feedback to team members and leads.
• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).
• Develop scripts to automate running timing analysis and generate reports.
• Collaborate with physical design engineers as well as RTL/Architecture teams.

Requirements

• BS + 6 years, MS + 4 years, or PhD + 2 years in Electrical Engineering or Computer Science.
• Expertise in timing analysis fundamentals.
• 1+ years of experience doing Static Timing Analysis.
• 1+ years of experience with timing constraint development.
• Experience with Timing Analysis using EDA tools (e.g., PrimeTime, Tempus, or others).
• Understanding of ASIC Physical Design from RTL-to-GDSII.
• Understanding of other sign-off activities (IR/EM, physical verification, DFT).
• 1+ years of scripting experience with Tcl, Perl, or Python.

Preferred Qualifications

• Experience in mentoring, leading, and coaching.
• Expertise developing flows using STA tools (e.g., PrimeTime, Tempus, or others).
• Expertise in ECO flows (e.g., PT-DMSA, Tempus-ECO, Tweaker, or others).
• Experience in advanced nodes (16nm or below).
• Expertise in parasitic extraction tools (e.g., STAR-RC, Quantus, or others).
• Expertise in circuit-level analysis using tools like SPICE/SPECTRE.
• Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die, etc.

Pay

• USA, CA, Cupertino: $157,300.00 - $212,800.00 USD annually
• USA, TX, Austin: $136,000.00 - $184,000.00 USD annually

Benefits

• Sign-on payments and restricted stock units (RSUs).
• Health insurance (medical, dental, vision, prescription, Basic Life & AD&D, and optional supplemental life plans).
• Employee Assistance Program (EAP) and mental health support.
• Medical Advice Line and Flexible Spending Accounts.
• Adoption and surrogacy reimbursement coverage.
• 401(k) matching.
• Paid time off and parental leave.

Learn more about our benefits at amazon.jobs/en/benefits.