Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

Key job responsibilities

• Develop & maintain flows for block and full-chip level static timing analysis
• Write, debug & validate timing constraints for blocks and full-chip
• Run Static Timing Analysis and give frequent feedback to team members and leads
• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues)
• Develop scripts to automate running timing analysis and generate reports
• Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams

Basic Qualifications

• Experience scripting or coding
• BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS
• Expertise in timing analysis fundamentals
• 1+ years doing Static Timing Analysis
• 1+ years with timing constraint development
• Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others)
• Understanding of ASIC Physical Design from RTL-to-GDSII
• Understanding of other sign-off activities (ir/em, physical verification, DFT)
• 1+ years of scripting experience with Tcl, Perl or Python

Preferred Qualifications

• Experience in mentoring, leading and coaching
• Expertise developing flows using STA tools (examples: PrimeTime, Tempus or others)
• Expertise in ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker or others)
• Experience in advanced nodes - 16nm or below
• Expertise in parasitic extraction tools (examples: STAR-RC, Quantus or others)
• Expertise on circuit level analysis using tools like SPICE / SPECTRE
• Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die etc.