Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland)

About the role

Fairwinds Technologies is a U.S.-based engineering firm specializing in SATCOM, RF Transmission Systems, Network Design, Systems Integration, and Digital Signal Processing (DSP). We support C4 systems in austere military environments, delivering advanced communications, networking, and IT solutions to defense and civilian agencies worldwide.

Key Responsibilities

• Design, implement, and verify FPGA logic using Verilog and VHDL within the Xilinx Vivado toolchain for Zynq UltraScale+ RFSoC, MPSoC and Versal devices.
• Develop programmable logic architectures for signal processing, control, and high-speed data movement applications.
• Implement complex DSP algorithms provided by DSP engineers into efficient FPGA fabric designs (filters, FFTs, channelizers, modulators, demodulators, decimation/interpolation, fixed-point optimization).
• Work with embedded software engineers to define and implement PL–PS interfaces, including AXI-Lite, AXI-Stream, DMA, interrupts, and register maps.
• Integrate FPGA designs with embedded processors and heterogeneous compute architectures (e.g., Zynq UltraScale+ MPSoC, RFSoC, Versal ACAP).
• Perform functional simulation, static timing analysis, and resource optimization to meet performance, latency, and power constraints.
• Support FPGA bring-up and debugging on custom PCB hardware using lab tools such as JTAG, Integrated Logic Analyzer (ILA), logic analyzers, and oscilloscopes.
• Participate in system integration and debug efforts spanning FPGA logic, embedded software, DSP algorithms, and hardware.
• Develop test benches, validation strategies, and design documentation, including FPGA design descriptions, interface control documents (ICDs), and SBIR deliverables as required.
• Support prototype-to-production transitions, including ECOs, version control, and configuration management.
• Design and integrate interfaces with high-speed data converters from Analog Devices (e.g., ADRV9009, AD9081) and Texas Instruments, including JESD204B/C and LVDS interfaces.
• Develop multi-sample per clock (parallel sample) architectures to meet throughput requirements for wideband RF signal processing applications.
• Apply fundamental RF signal processing knowledge to support digital front-end design including NCOs, mixers, digital up/down conversion, and gain control.

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in FPGA design and development.
• Strong proficiency in Verilog and/or VHDL.
• Deep experience with RTL simulation tools such as Siemens Questa and Vivado Simulator.
• Hands-on experience using Xilinx Vivado for synthesis, implementation, timing closure, and debug.
• Hands-on experience with Xilinx Zynq UltraScale+ RFSoC a must; experience with Versal devices and other devices within the UltraScale+ family strongly preferred.
• Experience developing FPGA designs for PCB-based embedded systems.
• Experience implementing complex DSP designs provided by DSP engineers, translating algorithm specifications into efficient RTL implementations.
• Strong understanding of AXI protocols, clock domain crossing (CDC), resets, and timing constraints.
• Experience with FPGA debug tools such as ILA, VIO, and JTAG-based debugging.
• U.S. Citizenship and an active DoD Secret (or higher) security clearance (or ability to obtain).
• Experience integrating FPGA designs with high-speed data converters from Analog Devices (e.g., ADRV9009, AD9081) or Texas Instruments AFE/ADC products.
• Experience designing multi-sample per clock (parallel sample) architectures for high-throughput signal processing.
• Fundamental understanding of RF signal processing concepts including sampling theory, digital mixing, filtering, and frequency conversion.

Additional Preferred Qualifications

• Experience with Versal ACAP architecture, including heterogeneous compute resources (PL, AI Engines, hardened blocks).
• Experience implementing or integrating high-speed interfaces (JESD204B/C, Ethernet, PCIe, Aurora, or similar) in RF data converter applications.
• Strong understanding of DSP concepts and fixed-/floating-point implementation tradeoffs in FPGA designs.
• Scripting experience (Tcl and/or Python) for build automation, constraints generation, and CI workflows.
• Experience supporting DoD SBIR projects or similar government-funded R&D efforts.
• Experience with Xilinx RFSoC integrated RF data converters and RF Data Converter IP.
• Familiarity with Analog Devices reference designs and evaluation platforms (e.g., ADRV9009-ZU11EG).

Work Environment

This position is primarily performed in a traditional office environment. Some remote/hybrid work is also possible.