SoC Systems Software Engineer, Annapurna Labs Machine Learning Accelerators, AWS

About the role

Develops SoC models and infrastructure to enable SoC validation, accelerate system software development, and enable architectural exploration.

Responsibilities

• Develop and own components of our SoC models, both single-chip and at the datacenter-scale level
• Debug complex hardware/software interactions across the full software stack — from register-level bring-up on functional models and emulators, to performance analysis on live silicon
• Collaborate with chip architects, RTL designers, modelers, compiler engineers, and ML framework teams to co-design and validate the hardware/software interface
• Contribute to the design of hardware features by providing a software perspective early in the chip development cycle
• Build tooling, test infrastructure, and automation that accelerates development for yourself and your teammates

Requirements

• Knowledge of hardware architectures
• 2+ years of professional experience developing firmware, drivers, runtime software, or low-level systems software for custom hardware (SoCs, ASICs, GPUs, CPUs, FPGAs)
• Experience programming in C++, Python, and/or Rust (preference for at least 2)

Qualifications

• Experience with collective communication libraries or distributed systems primitives (MPI, NCCL, RCCL, or similar)
• Experience debugging using functional models, QEMU, FPGA, or emulators
• Experience with Linux kernel development, device drivers, or bare-metal firmware
• Familiarity with PCIe, DMA engines, on-chip interconnects, or network-on-chip architectures
• Experience with performance profiling and optimization of latency-sensitive software
• Experience with multi-threaded, multi-process, or asynchronous programming models

Skills

• Comfortable reading hardware specs and translating them into working software
• Experience debugging problems where the root cause could be in hardware, software, or the interface between them
• Experience building firmware, drivers, runtime software, or communication libraries for SoCs, ASICs, GPUs, CPUs, or FPGAs
• Care about performance and have experience profiling and optimizing latency-sensitive or throughput-critical code paths
• Comfortable in C++ close to the hardware and use Python for tooling and automation
• Enjoy working on a small, high-impact team where you own significant pieces of the stack end-to-end

Benefits

• Comprehensive benefits including health insurance, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage
• 401(k) matching
• Paid time off
• Parental leave

Pay

Base salary range: $143,700.00 - $194,400.00 USD annually

Schedule

Based in either Cupertino, CA or Austin, TX