SoC Firmware Engineering Manager, Annapurna Labs Machine Learning Acceleration, AWS

About the role

When a new Trainium or Inferentia chip comes back from the fab, our code is the first software to touch it. We're looking for a hands-on engineering manager who lives and breathes low-level software — someone who's debugged register-level issues at 3am and wants to build a team that does it better.

Responsibilities

• Manage, coach, and grow a team of 6 engineers — set technical direction, own hiring, and create an environment where strong engineers want to stay
• Cook up deliverables across chip architects, RTL designers, verification engineers, validation engineers, and platform software teams — you're the single point of accountability for HAL readiness on every new chip program
• Bring up for new SoC tape-outs, from first-silicon power-on through production fleet deployment
• Prioritize work across multiple concurrent chip programs and customer teams, balancing urgent bring-up needs against long-term architecture investments
• Drive the architecture of our C++ template metaprogramming framework, BUTR (Built-in Unit Test for Registers), and HITL (Hardware-in-the-Loop) test infrastructure
• Ship the same C++ codebase to three execution environments: SystemVerilog DPI for chip verification, QEMU for emulation, and Carbon OS on embedded microcontrollers for production fleet
• Get into the weeds alongside your team — debug register-level HW/SW interactions, review code, and write code yourself when it matters
• Your pre-silicon software runs in simulation and emulation months before real silicon arrives. When the chip comes back from the fab, you validate those predictions on real hardware — and when they don't match, you figure out whether it's a silicon bug or a software bug.

Requirements

• 3+ years of engineering team management experience
• 7+ years of professional software development in C or C++, including embedded, firmware, or systems-level development
• 4+ years of designing or architecting software systems (abstraction layers, hardware/software interfaces)
• Experience developing software that interfaces directly with hardware: SoC, ASIC, FPGA, or embedded microcontrollers
• Experience with register-level programming and hardware debug (waveform analysis, bus-level tracing, or similar)

Qualifications

• Basic Qualifications: 3+ years of engineering team management experience, 7+ years of professional software development in C or C++, including embedded, firmware, or systems-level development, 4+ years of designing or architecting software systems (abstraction layers, hardware/software interfaces), Experience developing software that interfaces directly with hardware: SoC, ASIC, FPGA, or embedded microcontrollers, Experience with register-level programming and hardware debug (waveform analysis, bus-level tracing, or similar)
• Preferred Qualifications: Experience in recruiting, hiring, mentoring/coaching and managing teams of Software Engineers to improve their skills, and make them more effective, product software engineers, Experience with silicon bring-up or pre/post-silicon software validation, Experience shipping software across multiple target platforms (simulation, emulation, production hardware), Familiarity with bus protocols (APB, AXI, PCIe) or memory subsystems (HBM, DDR), Experience with C++ template metaprogramming or code generation frameworks, Experience building or maintaining hardware abstraction layers or board support packages

Benefits

No ML background needed. Your firmware is the foundation that enables ML training across clusters of thousands of interconnected accelerators — you'll work on components like PCIe and HBM, but won't need to understand ML itself.

This role can be based in Cupertino, CA or Austin, TX. The team is split between the two sites.

Location

• Cupertino, CA
• Austin, TX

Pay

• USA, CA, Cupertino - 212,700.00 - 287,700.00 USD annually
• USA, TX, Austin - 184,900.00 - 250,200.00 USD annually

Schedule

• Full-time