SoC Firmware Engineering Manager, Annapurna Labs Machine Learning Acceleration, AWS

About the role

The SoC Firmware Engineering Manager at Annapurna Labs, working with AWS, oversees the firmware that initializes and manages the hardware blocks on custom ML accelerator chips. This role involves managing a team of engineers, coordinating with various teams, and ensuring the software is correct down to individual register bits.

Responsibilities

• Manage, coach, and grow a team of 6 engineers
• Coordinate deliverables across chip architects, RTL designers, verification engineers, validation engineers, and platform software teams
• Own bring-up for new SoC tape-outs, from first-silicon power-on through production fleet deployment
• Prioritize work across multiple concurrent chip programs and customer teams
• Drive the architecture of the C++ template metaprogramming framework, BUTR (Built-in Unit Test for Registers), and HITL (Hardware-in-the-Loop) test infrastructure
• Ship the same C++ codebase to three execution environments: SystemVerilog DPI for chip verification, QEMU for emulation, and Carbon OS on embedded microcontrollers for production fleet
• Debug register-level HW/SW interactions, review code, and write code yourself when it matters

Requirements

• 3+ years of engineering team management experience
• 7+ years of professional software development in C or C++, including embedded, firmware, or systems-level development
• 4+ years of designing or architecting software systems (abstraction layers, hardware/software interfaces)
• Experience developing software that interfaces directly with hardware: SoC, ASIC, FPGA, or embedded microcontrollers
• Experience with register-level programming and hardware debug (waveform analysis, bus-level tracing, or similar)

Qualifications

• No ML background needed
• Experience in recruiting, hiring, mentoring/coaching and managing teams of Software Engineers to improve their skills, and make them more effective, product software engineers
• Experience with silicon bring-up or pre/post-silicon software validation
• Experience shipping software across multiple target platforms (simulation, emulation, production hardware)
• Familiarity with bus protocols (APB, AXI, PCIe) or memory subsystems (HBM, DDR)
• Experience with C++ template metaprogramming or code generation frameworks
• Experience building or maintaining hardware abstraction layers or board support packages