SoC Physical Design Verification Engineer

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.

What We Need

• BS or MS in Engineering (Electrical, Electronics, or related field).
• 7–14 years of hands-on experience in CPU/IP/SoC physical verification.
• Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification.
• Solid understanding of advanced node challenges (7nm, 5nm, 3nm) and FinFET design considerations.
• Scripting proficiency (Python, TCL) for automation and flow optimization.
• Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.

Pay

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets.

Schedule

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO.

Benefits

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.