SoC Chip Lead

About the role

We are seeking a SoC Chip Lead with deep technical expertise and a track record of delivering complex silicon from concept to production. You will architect and implement high-quality IP across Configuration, Security, Processor, Memory, and High-Speed interfaces, translating system and architectural requirements into micro-architecture and RTL. You will provide technical leadership across cross-functional teams, drive continuous improvements in IP performance and integration, and shape Lattice's next-generation SoC roadmap.

Responsibilities

• Lead development of MCMs with FPGA and ASSPs utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures across multiple program generations
• Own chip tapeout and chip signoff with full accountability for chip quality
• Drive cross-functional technical leadership across multiple sites; translate product requirements into clear priorities, tradeoffs, and execution paths
• Partner with architects, RTL engineers, and software teams to evaluate architecture tradeoffs and drive hardware design decisions across the SoC
• Lead cycle-approximate performance modeling to enable architectural exploration ahead of RTL availability and accelerate early software development
• Quantify system-level tradeoffs across compute, memory bandwidth, and on-chip interconnect to shape reference architectures and inform long-term silicon strategy
• Own system-level debug spanning floor-planning, power distribution, clocking, timing closure, and SI/PI
• Engage with leading IP vendors to define and execute the IP roadmap; conduct competitive benchmarking
• Present project status and technology roadmaps to executive leadership, with a focus on new growth markets and opportunities
• Apply agentic AI methodologies to scale and accelerate design execution

Required Qualifications

• BS/MS/PhD in Electrical or Computer Engineering with 20+ years of FPGA/SoC design experience
• Established track record leading programs from concept to tape-out and production release
• Expertise in SystemVerilog, synthesis, and static timing analysis
• Deep expertise across SoC domains including High-speed interfaces, System Interconnects, Processor subsystems, and 2.5D/3D packaging and chiplet-based architectures
• Own system-level functional and performance modeling across SoC subsystems, ensuring RTL correlation and supporting emulation-based pre-silicon validation
• Define and own DFx methodology including scan, BIST, and manufacturing test from IP to chip level
• Experience debugging complex use cases through verification, emulation, and system validation
• Demonstrated ability to lead and grow geographically distributed, cross-functional engineering teams
• Strong written and oral communication skills with a history of executive-level presentations

Pay

Base Pay Range: 248400. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity.

Benefits

This role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more.