Silicon Packaging Engineering Manager

Key Responsibilities

• Lead and manage a group of IC Packaging Engineers, providing guidance, mentorship, and support to ensure the successful execution of projects.
• Oversee the planning, scheduling, and execution of package design projects, ensuring that milestones and deadlines are met.
• Foster a collaborative and innovative team environment, encouraging continuous learning and professional development.
• Lead design groups, coordinating efforts across multiple teams to achieve project goals.

Technical Expertise

• Serve as the primary package design technical lead and guide customers through end-to-end package design flow.
• Drive the development of advanced packaging designs, ensuring compliance with industry standards and best practices.
• Collaborate with cross-functional teams, including package architects, silicon and board design teams, design rule owners, electrical analysis engineers, and integration teams to define and implement design specifications.
• Leverage extensive experience in advanced packaging designs to meet design KPIs.
• Ensure products are designed and developed with high quality standards by overseeing design processes, risk management, and compliance throughout the product design lifecycle, working closely with cross-functional teams to identify and address potential quality issues before they arise.

Project Management

• Develop and maintain detailed project plans, including resource allocation, risk management, and progress tracking.
• Cook up with stakeholders to ensure alignment on project goals, deliverables, and timelines.
• Conduct regular project reviews and provide status updates to senior management.

Innovation and Improvement

• Identify and implement process improvements to enhance the efficiency and quality of package designs and development.
• Stay current with industry trends and emerging technologies, incorporating new methodologies and tools into the design process.
• Drive innovation in product design, exploring new approaches and techniques to achieve competitive advantages.

Qualifications

• Minimum qualifications: Bachelor's degree in Electrical Engineering or STEM related field with 9+ years of relevant experience OR Master's degree in Electrical Engineering or STEM related field with 6+ years of relevant experience OR PhD in Electrical Engineering or STEM related field with 4+ years of relevant experience.
• Relevant experience should include the following: Experience in IC Package, chiplet/SOC design, or heterogenous integration, with at least 3 years in a leadership role. Proven experience in a leadership or management role, with a track record of successfully leading engineering teams and delivering complex projects within established timelines. Experience in performance/manufacturability/yield aware design methodologies. Experience with design flows and methodologies (physical design, analysis, verification). Experience working with IC Packaging EDA tools from Siemens and/or Cadence. Experience with packaging technologies and heterogenous integration.
• Preferred qualifications: Experience with IC Packaging designs for HPC/AI class of products.

Pay

Annual Salary Range for jobs which could be performed in the US: $190,610.00 - 269,100.00 USD

Schedule

Shift 1 (United States of America)

Location

Primary Location: US, Arizona, Phoenix

Additional Locations

• US, California, Santa Clara
• US, Oregon, Hillsboro