Senior System Integration Engineer, Memory

Hire Process

This position is for an existing vacancy.

About the Role

The Senior Memory Systems Engineer will own HBM and LPDDR integration in sophisticated SoCs, covering the full stack from silicon to product release. This role requires hands-on experience in system-level memory challenges, from bringup to product readiness.

Responsibilities

• HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs.
• Full-Stack Memory Closure: Ensure memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware.
• Post-Silicon Margining, VF Shmoo & Correlation: Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency.
• Memory Debug: Train, calibrate, SI/PI & stability: Debug and resolve memory training, calibration, SI/PI, and system-level stability issues.
• Validation & Characterization Planning: Define validation, characterization, and issue-tracking plans across chip programs.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering, or equivalent experience.
• 12+ years of experience in HBM, LPDDR, or high-speed memory systems, with hands-on depth in silicon bringup, characterization, and debug at scale.
• Deep command of SI/PI, timing, margining, and memory training behavior, and the ability to work across design, package, firmware, validation, and product teams.
• Experience with HBM3/HBM3E specifics, specific JEDEC margins, thermal-electrical co-sim, ECC methodology & power management is highly desired.
• Experience with AI-assisted debugging, test automation, and architecture exploration.

Qualifications

• Experience with AI-assisted debugging, test automation, and architecture exploration.
• Experience with LLM-assisted tools and ML models for pattern matching and root cause analysis.
• Experience with intelligent test and validation automation.
• Experience with HBM3/HBM3E specifics, specific JEDEC margins, thermal-electrical co-sim, ECC methodology & power management.

Benefits

NVIDIA offers competitive compensation, including a base salary range of $196,000 - $310,500, along with equity and benefits.

Pay

Base salary will be determined based on location, experience, and the pay of employees in similar positions.

Schedule

Applications for this job will be accepted at least until August 29, 2026.