Senior System Integration Engineer, Memory

About the Role

NVIDIA's Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team drives tradeoff analysis, system integration, and POR alignment across the organization. We're seeking a Senior Memory Systems Engineer to own HBM and LPDDR integration in sophisticated SoCs, covering the full stack from silicon to product development.

Responsibilities

• HBM & LPDDR System Integration and Bringup: Drive system integration, bringup, characterization, and debug for next-generation SoCs, taking memory subsystems from first silicon to production-ready scale.
• Full-Stack Memory Closure: Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware, translating characterization results into signed-off operating points and release criteria.
• Post-Silicon Margining, VF Shmoo & Correlation: Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency, building the characterization foundation for product decisions.
• Memory Debug: Resolve memory training, calibration, SI/PI, and system-level stability issues, leveraging cross-domain expertise.
• Validation & Characterization Planning: Define validation, characterization, and issue-tracking plans across chip programs, ensuring comprehensive testing and data collection.

Requirements

• BS or MS in EE/CE or equivalent experience.
• 12+ years in HBM, LPDDR, or high-speed memory systems, with hands-on silicon bringup, characterization, and debug experience.
• Deep understanding of SI/PI, timing, margining, and memory training behavior, with multi-functional fluency across design, package, firmware, validation, and product teams.

Qualifications

• PHY controller development experience is a significant plus.
• Familiarity with HBM PHY and controller architecture, with a system-level instinct to anticipate and resolve memory-related product issues.

Skills

• AI-Accelerated Debug & Root Cause Analysis: Experience with LLM-assisted tools and ML models for failure signature analysis and root cause detection.
• HBM3/HBM3E Expertise: Knowledge of HBM3/HBM3E specifics, JEDEC margins, thermal-electrical co-sim, ECC methodology, and power management.
• Test & Validation Automation: Ability to automate data collection, test sequencing, and results analysis for characterization programs.
• LLM-Assisted Architecture Exploration: Experience using LLMs for architecture exploration, spec navigation, and trade-off analysis.

Pay

The base salary range for this role is $196,000 - $310,500 USD, determined by location, experience, and internal pay equity. Equity and benefits are also included.