Senior System Integration Engineer, Memory

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology and amazing people. Today, we're harnessing the boundless possibilities of AI to build the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. The Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team drives tradeoff analysis, system integration, and POR alignment across the entire organization. This is where ideas become chips, and chips become products that define the state of the art.

About the role

We're looking for a Senior Memory Systems Engineer to own HBM and LPDDR integration in sophisticated SoCs. This role covers the full stack, including silicon, package, embedded software, testing, and product development. The engineer will resolve the toughest system-level memory challenges throughout the process, building solutions that hold up at scale.

Responsibilities

• HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs — taking memory subsystems through the full arc from first silicon to production-ready at scale.
• Full-Stack Memory Closure: Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware — translating characterization results into signed-off operating points and release criteria that the full program depends on.
• Post-Silicon Margining, VF Shmoo & Correlation: Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency — building the characterization foundation that underpins every product decision downstream.
• Memory Debug: Training, Calibration, SI/PI & Stability: Debug and resolve memory training, calibration, SI/PI, and system-level stability issues — the class of problems that sit at the intersection of electrical, physical, and software behavior and demand deep cross-domain expertise to resolve at scale.
• Validation & Characterization Planning: Define validation, characterization, and issue-tracking plans across chip programs — building the framework that ensures the right tests exist, the right data gets collected, and issues are tracked with enough fidelity to close.
• AI-Accelerated Debug & Root Cause Analysis: Use LLM-assisted tools and ML models to pattern-match failure signatures across VF shmoo, eye diagrams, and margining datasets — converging on root cause and outlier detection faster than manual triage, with engineering judgment setting the bar for what the model can decide.
• Intelligent Test & Validation Automation: Automate data collection, test sequencing, and results analysis across characterization programs — cutting cycle time from silicon arrival to product-ready data and freeing bandwidth for problems that require human expertise.
• LLM-Assisted Architecture & Trade-Off Exploration: Accelerate architecture exploration, spec navigation, and cross-domain trade-off analysis using LLMs — surfacing precedents from prior programs and building characterization plans for expert review.

Requirements

• BS or MS in EE/CE — or equivalent experience.
• 12+ years in HBM, LPDDR, or high-speed memory systems, with hands-on depth in silicon bringup, characterization, and debug at scale. PHY controller development experience is a significant plus.
• Deep command of SI/PI, timing, margining, and memory training behavior — and the multi-functional fluency to work across design, package, firmware, validation, and product teams without losing the thread.
• HBM PHY and controller architecture familiarity is useful context, but the role demands system-level instinct to see where memory behavior is about to become a product problem — and the inventiveness to resolve it before it does.

Skills

• Experience with HBM3/HBM3E specifics, specific JEDEC margins, thermal-electrical co-sim, ECC methodology & power management is highly desired.

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 196,000 USD - 310,500 USD. You will also be eligible for equity and benefits.