Senior Staff RTL Design Engineer- 16908

Job Description

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

• Extensive ASIC digital design experience with a track record of delivering production RTL for complex semiconductor IP
• Expert Verilog proficiency for timing-critical designs
• Strong Perl scripting skills for design automation
• Deep knowledge of synthesis, timing analysis, and power optimization
• Experience with PHY IP or high-speed interfaces is preferred

What You'll Be Doing

• Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
• Optimize designs to meet timing, power, and area targets across multiple process nodes
• Develop Perl automation for design generation and flow integration
• Collaborate with cross-functional teams to resolve timing and power challenges
• Contribute to design reviews and methodology development

The Impact You Will Have

• Your designs will enable LPDDR PHY IP deployed in high-volume mobile, automotive, and AI products
• You will contribute to a major revenue-generating product line for Synopsys
• Your work will define performance characteristics for customer systems-on-chip
• Your automation will improve design efficiency across the engineering team
• Your expertise will influence architectural decisions for future products

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of ASIC digital design experience with RTL ownership in production silicon
• Expert Verilog proficiency for timing-critical designs
• Strong Perl scripting skills for design automation
• Deep knowledge of synthesis, timing analysis, and power optimization
• Experience with PHY IP or high-speed interfaces is preferred

Who You Are

• You understand how RTL structure affects timing and power outcomes
• You communicate effectively across technical disciplines
• You produce maintainable code that supports collaboration
• You identify process improvements proactively
• You resolve technical issues through systematic analysis

The Team You'll Be Part Of

You will join the team responsible for microarchitecture and front-end design of LPDDR PHY IP. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.

Rewards and Benefits

• Comprehensive health, wellness, and financial benefits
• Annual bonus, equity, and other discretionary bonuses
• Retirement plans
• Competitive salaries

Benefits

• Health & Wellness
• Time Away
• Family Support
• Retirement Plans
• Compensation