Senior RTL Design Engineer

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Define the detailed microarchitecture specifications for silicon subsystems and small to medium-sized intellectual property blocks to meet performance, area, and power requirements.
• Integrate internal and external intellectual property (IP) blocks seamlessly into complex silicon designs and multi-component subsystems.
• Execute production-grade RTL coding, debug intricate function and performance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks.
• Partner closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip-level design verification.
• Drive technical alignment across multi-disciplinary and multi-site engineering groups to resolve architectural issues and ensure successful product delivery.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience with IP Development or Integration.
• Experience in ASIC development with Verilog or VHDL (VHSIC Hardware Description Language).
• Experience with a scripting language (e.g., Python or Perl).

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
• Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
• Knowledge of high-performance and low-power design techniques.
• Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design.
• Knowledge of FPGA and emulation platforms.

Pay

US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits