Senior Staff Design Verification Engineer

About the role

We are seeking a Senior Staff Design Verification Engineer to join our team. The ideal candidate will have a strong background in electrical engineering, computer science, or a related field with extensive experience in SoC verification.

Responsibilities

• Build and lead the verification environment from architecture to tape-out
• Develop and implement verification methodologies including UVM/OVM
• Design and execute design verification tests and debug complex issues
• Work closely with the team to ensure successful project completion
• Collaborate with cross-functional teams to deliver high-quality products

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or related field with 12+ years of industry experience
• Master's degree in Electrical Engineering, Computer Science, or related field preferred with 7+ years of industry experience
• Experience in SoC verification cycle from architecture to tape-out to bring up
• Good knowledge of verification methodologies such as UVM/OVM
• Hands-on ASIC-SoC Design verification tests and debug experience
• Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology
• Good problem-solving skills and passion for tackling challenges in the AI domain
• Experience with SystemVerilog and verification methodologies (UVM/OVM/VMM)

Qualifications

• Passionate about AI and thrive in a fast-paced and dynamic startup culture
• Preferred: Experience with C/C++, SystemC
• Successfully led creation/implementation of multiple SoC verification environments and tape-out efforts

Skills

• SystemVerilog
• Verification Methodologies (UVM/OVM/VMM)

Benefits

Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions.

Pay

Commensurate with experience

Schedule

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week