Senior Speed Characterization Engineer - Silicon Co-Design Group

What You'll Be Doing

• Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space.
• Close the correlation gap. Tie pre-silicon timing analysis and critical path predictions to measured silicon, quantify where the model diverges from reality, and produce analysis that architecture and design can act on with confidence.
• Trace failures to their source, whether a microarchitectural bottleneck, a critical path that doesn't close under voltage, a clocking issue, or a process corner the model didn't anticipate, and drive the resolution.
• Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing difficulty. Know where AI accelerates real work and where it introduces risk.
• Sit at the decision table. Your data surfaces tradeoffs across architecture, VLSI, ASIC, firmware, and product teams. Your analysis is what settles calls.

What We Need To See

• BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience.
• 5+ years with hands-on silicon: bring-up, post-silicon speed validation, frequency characterization, or timing analysis on real hardware.
• Strong computer architecture fundamentals including pipeline structures, clocking, memory hierarchies, and how microarchitectural decisions propagate into frequency and power.
• Depth in static timing analysis, critical path identification, and the ability to read and reason about timing reports at the block and chip level.
• Enough design intuition to know what you're measuring and enough statistical fluency to know what the data means.
• Proficiency in silicon margining, guard-banding, and PVT/binning dependencies.
• Scripting depth in Python, Perl, or C/C++. You build the tools your work depends on.

Ways To Stand Out From The Crowd

• You've closed the prediction-to-silicon loop with a correlation methodology precise enough that other teams adopted it.
• You've traced a frequency miss to a specific critical path, microarchitectural interaction, or process corner and driven the fix all the way through.
• Built or deployed AI-driven flows for characterization or analysis, and can speak to both the outcome and the guardrails you put in place.
• Background is in datacenter-scale or high-performance silicon and you know how complexity at scale changes the failure landscape and raises the cost of being wrong.

Pay

Base salary range: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.