Senior Silicon Engineer

About the role

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

Responsibilities

• Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows.
• Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across MMMC corners.
• Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements.
• Run, review and debug physical design flows, timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations.
• Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA.
• Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership.

Qualifications

Required Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

• 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT)
• 8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs
• Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints
• Experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)
• Proficiency in recent synthesis tool capabilities and methods for QoR improvement
• Proficiency in static timing analysis
• Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification
• Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines
• Proficiency in translating physical design results into feedback for flow or RTL improvement
• Proficiency in Tcl, Python
• Knowledge of full RTL2GDS flow

Other Requirements

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Pay

The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.