Senior Silicon Physical Design Engineer - TeraWave

About the role

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. We are seeking a Senior Silicon Physical Design Engineer to design and develop advanced integrated circuits for our revolutionary space-based communications network.

Responsibilities

• Execute RTL-to-GDS physical implementation of SoCs for space applications: synthesis, floor-planning, power and clock distribution, place and route, and timing closure
• Drive full signoff closure: STA, physical verification (DRC/LVS/ERC), logic equivalence checking (LEC), and EM/IR analysis
• Debug timing violations and implement timing and functional ECOs
• Perform partition- and chip-level physical verification for mixed-signal designs, including analog/digital integration checks
• Develop and maintain PV runsets, signoff decks, and flow automation for repeatable top-level verification
• Implement DFT structures and methodologies
• Collaborate with front-end and analog/mixed-signal teams to preserve design intent through implementation and signoff
• Interface with foundries on design-rule compliance, manufacturability, and yield
• Document design and verification methodologies and results
• Support post-silicon validation and debugging activities

Requirements

• B.S. degree in Electrical Engineering, Computer Engineering, or related field
• 7+ years of experience in physical design of ASICs
• Experience with industry-standard EDA tools for physical design (Cadence, Synopsys, Siemens or Mentor)
• Hands-on experience across the RTL-to-GDS flow, including timing closure and power/noise analysis
• Proficiency in Python, Tcl, and Makefiles
• Signoff and closure experience: Static Timing Analysis(STA), Physical Verification (PV), Logic Equivalence Checking (LEC), and Electromigration & IR drop (EM/IR)
• Understanding of timing closure and signal integrity challenges
• Experience with power analysis and optimization techniques

Qualifications

• Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
• Experience developing ASICs that meet stringent space-qualification standards for performance, reliability, and efficiency
• Knowledge of radiation-hardened design methodologies
• Experience with advanced process nodes (16nm and below)
• Background in high-speed digital design (>1GHz)
• Experience with 3D packaging or chiplet technologies
• Understanding of thermal considerations in ASIC design
• Familiarity with space qualification requirements for electronic components
• Experience with low-power design techniques for battery or solar-powered systems

Skills

• Expertise in physical design methodologies, and semiconductor technologies
• Proven ability to thrive in a fast-paced environment where innovation meets mission-critical execution

Benefits

• Medical, dental, vision, basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with a company match of up to 5%
• Education Support Program
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays

Pay

Base Pay Range For CA applicants is $230,398.00 - $322,556.85 WA applicants is $230,398.00 - $322,556.85 Other Site Ranges May Differ

Schedule

This role is based on site in Austin, TX; San Diego, CA; the Bay Area, CA; or Renton, WA. A temporary remote work exception is approved while our Bay Area, Austin, and/or San Diego sites are being developed.