Senior SI/PI Engineer - AI and Compute Server Design

Core Responsibilities

• Perform pre- and post-layout SI analysis for high-speed interfaces including PCIe Gen5/Gen6, CXL, NVLink, Ethernet/SerDes, and DDR5/DDR6 memory, defining channel budgets, routing rules, and equalization strategies.
• Design and validate power delivery networks, including PDN impedance targeting, decoupling strategy, and IR-drop analysis for high-current GPU, CPU, and VR rails.
• Build and run models using tools such as HFSS, ADS, HSPICE, Sigrity, or equivalent; develop IBIS-AMI and S-parameter-based channel simulations.
• Execute measurements with high-speed oscilloscopes, VNAs, TDRs, and BER testers; correlate simulation to lab data and drive corrective design changes.
• Partner with board designers, layout, and mechanical teams to embed SI/PI rules into stackups, routing, and connector/cable selection, and support EVT/DVT/PVT bring-up and debug.

Required Qualifications & Skills

• Education: Bachelor's or Master's in Electrical Engineering or a related field.
• Experience: 6+ years of hands-on SI/PI experience for servers, GPU platforms, or high-speed digital systems, with proven delivery of designs into production.
• Technical expertise: Strong knowledge of high-speed channel design, PDN design and analysis, connector/cable modeling, and PCB stackup/materials; proficiency with SI/PI simulation tools (e.g., HFSS, ADS, HSPICE, Sigrity) and high-speed lab measurement equipment.
• Standards: Familiarity with PCIe, CXL, DDR JEDEC, and Ethernet electrical specifications and compliance methodologies.
• Communication: Able to translate analysis into clear, actionable design guidance and collaborate effectively across board, layout, and mechanical teams.

Pay

$127,000 to $170,000