Senior Security IP Engineer

About the role

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE delivers design, development, manufacturing, and packaging of Microsoft's state-of-the-art computer chips, including the Azure Cobalt. The Shared and Custom IP & Silicon (SCIPS) team defines and delivers operational measures of success for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability related to Microsoft cloud hardware.

Responsibilities

• Own end-to-end development of security IPs from architecture and microarchitecture definition through silicon validation.
• Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality IP solutions.
• Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle.
• Lead design signoff activities including CDC, RDC, LINT, synthesis, STA, and timing closure.
• Implement and integrate hardware security technologies such as cryptographic accelerators, root-of-trust, secure boot, and key management.
• Drive pre-silicon and post-silicon debug, silicon bring-up, and root-cause analysis of complex system issues.
• Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements.

Qualifications

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
• OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
• OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
• OR equivalent experience.

Screening Requirements:

• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role requires access to export-controlled information; proof of citizenship, U.S. residency, or other protected status is required for eligibility.

Preferred Qualifications:

• 8+ years of hardware design experience
• Expertise in Digital Design including microarchitecture specification development and RTL coding
• Expertise in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and LINT closure
• Experience in developing/optimizing high-speed CMOS designs and evaluating PPA tradeoffs
• Proficiency in Verilog, System Verilog, and scripting languages such as Python or Perl
• Design knowledge of industry-standard bus interfaces such as AMBA AXI protocol
• Experience in basic floor planning, static timing analysis/closure, and engaging with physical design teams
• Experience driving chip design quality through design and checklist reviews
• Strong communication and collaboration skills across teams
• Experience with leading-edge technologies (5 nm or newer)
• Experience with Cryptography Standards (e.g., AES, SHA, Elliptic Curve Cryptography) is a plus.

Pay

• Typical base pay range across the U.S.: USD $119,800 - $234,700 per year.
• Base pay range for the San Francisco Bay area and New York City metropolitan area: USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Additional pay and benefits information: Microsoft Careers Pay Information.