Senior Principal Engineer Digital ASIC Design/Manager

About the role

Exempt: Yes
Safety Sensitive: No
Department: TUBIS
Reports To: Not indicated

Responsibilities

• Lead digital design projects from inception to production for mixed signals ICs.
• Hire and manage full-time employees or contractors to support projects.
• Participate in RFIC design flow by architecting and designing digital control functionality which interfaces to I/O and analog functions.
• Perform RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, AMBA bus, state machine, memories, embedded processor cores (RISC-V), bus arbitration, DMA, registers, IO pads, synchronous, asynchronous access and control functions.
• Drive methodology process and requirement specification documents.
• Work with external vendors and internal teams in developing plans for micro-architecture, verification, and emulation of digital modules.
• Oversee PNR and ensure integrity of physical layer design.
• Perform/oversee test plan development, digital verification, coverage analysis, and post silicon lab test.
• Support mixed signal verification of design.
• Perform/oversee scan insertion, MBIST and LBIST.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed signal verification of design.
• Support mixed