Senior Physical Design Methodology Engineer, PPA Fusion Compiler

About the role

NVIDIA is looking for a Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join the Networking Silicon engineering team, developing high speed communication devices with the highest throughput and lowest latency.

What You Will Be Doing

• Developing efficient physical design methodologies for implementation of graphics processors and SOCs
• Developing unique and creative solutions to state-of-the-art physical design problems to improve PPA
• Formulating and developing ML-based solutions
• Participating in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis, and back-end verification across multiple projects
• Chip floorplan, power and clock distribution, chip assembly
• Data-based analysis and algorithmic solutions for PPA check and improvement

What We Need To See

• MS in Electrical, Computer Engineering, Computer Science (or equivalent experience)
• 10+ years' experience in Physical Design Engineering with ML-based solution development experience
• Proven implementation of ML-based solutions
• Familiarity with aspects of chip design including floor planning, clock and power distribution, place and route, integration and verification
• Strong knowledge of physical design with convergence in timing/EM/IR with best PPA
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence
• Familiarity with various process-related design issues including design for yield and manufacturability, EM and IR closure, and thermal management
• Solid understanding of standard industry PnR tools and analysis tools
• Capable of extensive scripting to check and improve PPA

Pay

• Base salary range: $168,000 - $264,500 USD for Level 4
• Base salary range: $196,000 - $310,500 USD for Level 5
• Also eligible for equity and benefits