Senior Physical Design Methodology Engineer, PPA Fusion Compiler

About the role

NVIDIA is seeking a Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our Networking Silicon engineering team. This team develops the industry's best high-speed communication devices, delivering the highest throughput and lowest latency.

Responsibilities

• Develop efficient physical design methodologies for graphics processors and System-on-Chips (SoCs).
• Develop unique and creative solutions to state-of-the-art physical design problems to improve Performance, Power, and Area (PPA).
• Formulate and develop ML-based solutions for flow and tool methodologies, including P&R, timing analysis, and closure.
• Conduct data-based analysis and algorithmic solutions for PPA checks and improvements.

Requirements

• Master’s degree in Electrical, Computer Engineering, or Computer Science (or equivalent experience).
• 10+ years of experience in Physical Design Engineering with ML-based solution development experience.
• Proven implementation of ML-based solutions.
• Familiarity with aspects of chip design, including Floor planning, Clock and Power distribution, Place and Route, Integration, and Verification.
• Strong background with hierarchical design approaches, top-down design, budgeting, timing, and physical convergence.
• Familiarity with various process-related design issues such as Design for Yield and Manufacturability, EM and IR closure, and thermal management.
• Experience with standard industry PnR tools and analysis tools, capable of extensive scripting to check and improve PPA.

Qualifications

• MS in Electrical, Computer Engineering, or Computer Science (or equivalent experience).
• 10+ years of experience in Physical Design Engineering with ML-based solution development experience.
• Proven implementation of ML-based solutions.
• Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Familiar with various process-related design issues including Design for Yield and Manufacturability, EM and IR closure, and thermal management.
• Experience with standard industry PnR tools and analysis tools, capable of extensive scripting to check and improve PPA.

Skills

• Experience with ML-based solutions for physical design.
• Strong understanding of standard industry PnR tools and analysis tools.
• Ability to script and automate PPA checks and improvements.
• Experience with hierarchical design and top-down design.
• Knowledge of process-related design issues such as Design for Yield and Manufacturability, EM and IR closure, and thermal management.

Benefits

• Competitive base salary ranging from $168,000 to $264,500 for Level 4, and $196,000 to $310,500 for Level 5.
• Equity and benefits package.

Pay

Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5.

Schedule

Full-time position.

Benefits

• Comprehensive health insurance plans.
• Flexible spending accounts.
• Retirement savings plans.
• Employee assistance programs.
• Professional development opportunities.

Application Instructions

Applications for this job will be accepted at least until May 24, 2026.

Equal Opportunity Employer

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.