Senior Physical Design Methodology Engineer, PPA Fusion Compiler

About the role

NVIDIA is seeking a Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join the Networking Silicon engineering team. The ideal candidate will be responsible for developing efficient physical design methodologies for graphics processors and System-on-Chips (SoCs), formulating and developing ML-based solutions, and participating in flow and tool methodologies for P&R, timing analysis, and closure.

Responsibilities

• Developing unique and creative solutions to state-of-the-art physical design problems to improve PPA
• Formulate and develop ML-based solutions
• Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis, and back-end verification
• Data based analysis and algorithmic solutions for PPA check and improvement

Requirements

• MS in Electrical, Computer Engineering, or Computer Science (or equivalent experience)
• 10+ years’ experience in Physical Design Engineering with ML-based solution development experience
• Proven implementation of ML-based solutions
• Familiarity with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence
• Familiarity with various process-related design issues including Design for Yield and Manufacturability, EM and IR closure, and thermal management
• Experience with standard industry PnR tools and analysis tools, capable of extensive scripting to check and improve PPA

Qualifications

• MS in Electrical, Computer Engineering, or Computer Science (or equivalent experience)
• 10+ years’ experience in Physical Design Engineering with ML-based solution development experience
• Proven implementation of ML-based solutions
• Familiarity with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification
• Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence
• Familiarity with various process-related design issues including Design for Yield and Manufacturability, EM and IR closure, and thermal management
• Experience with standard industry PnR tools and analysis tools, capable of extensive scripting to check and improve PPA

Skills

• Experience with ML-based solutions
• Strong background in physical design
• Understanding of chip design processes
• Ability to analyze and improve PPA

Benefits

• Competitive base salary ranging from $168,000 to $264,500 for Level 4, and $196,000 to $310,500 for Level 5
• Equity and benefits package

Pay

• Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5

Schedule

• Full-time position

Benefits

• Comprehensive health insurance
• Retirement savings plan
• Flexible work arrangements
• Professional development opportunities

Contact Information

If you are interested in this position, please apply at the provided link or contact us at [insert contact details here].