Senior Physical Design Engineer (CPU)

About the role

Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies.

Responsibilities

• Own physical design and implementation of CPU core blocks or subsystems
• Execute synthesis, floorplanning, place and route, and design closure
• Perform static timing analysis (STA), power analysis, and physical verification
• Drive convergence of timing, power, and area (PPA) metrics
• Debug and resolve complex design issues across multiple design stages
• Develop and optimize design flows and automation scripts
• Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams
• Contribute to improving design methodologies and best practices
• Provide guidance to junior engineers where applicable

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor’s in Computer / Electrical Engineering or related field with 7+ years of relevant work experience, or a Master’s in the same field with 4+ years of relevant work experience
• Experience with integrated circuit design tools (e.g., Synopsys/Cadence), including logic synthesis, place and route, static timing analysis, and design closure
• PV convergence (including static timing and power analysis)
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise, and electromigration checks
• Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g., Perl, Python, Ruby)
• Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Preferred Qualifications

• Industry experience/exposure with CPU Micro-Architecture
• Physical design best known practices concerning floor-planning, routing techniques, clock distribution
• Static Timing Analysis, Noise analysis, and reliability verification techniques
• RTL to GDS methodologies and formal equivalence
• Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus)

Skills

• Strong problem-solving and analytical thinking
• Takes ownership and accountability for deliverables
• Collaborates effectively across multidisciplinary teams
• Communicates technical concepts clearly and concisely
• Prioritizes work effectively in a fast-paced environment
• Continuously learns and applies new tools and methodologies

Why Join Us

• Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide
• Be part of a team driving innovation at advanced semiconductor process nodes
• Contribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design
• Collaborate with experienced engineers across architecture, design, and full-chip integration
• Grow your technical expertise through challenging problems, modern tools, and continuous learning opportunities
• Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology

Benefits

Intel offers a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. See Intel Benefits for more details.

Pay

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - $269,100.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role will require an on-site presence (Shift 1 in the United States of America). Primary location: US, Oregon, Hillsboro. Additional locations may apply.