Senior CPU Physical Design Engineer
In most instances, this position requires in‑person interviews as part of the hiring process.
Preferred working locations: Austin, TX, USA; Mountain View, CA, USA.
About the role
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct‑to‑consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, software, and hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, aiming to improve people's lives through technology.
Responsibilities
- Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade‑offs.
- Own block and IP‑level physical design implementation from synthesis through place and route.
- Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
- Execute sign‑off activities, including static timing analysis, power recovery, and electrical layout checks.
Minimum qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with high‑speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
- Experience with sign‑off convergence domains, including static timing analysis (STA), electrical checks, or physical verification.
Preferred qualifications
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- Experience with advanced process nodes (e.g., 5 nm, 3 nm, 2 nm, or below).
- Experience applying AI/ML‑assisted techniques for physical design closure and PPA scaling.
- Proficiency in scripting (Python, Tcl, Perl) and data mining for QoR metrics.
- Understanding of EMIR flows, power‑grid design, and design reliability for high‑frequency circuits.
Pay
US: $163,000 – $236,000 (USD) + 15 % bonus target + equity + benefits.