Senior Mixed-Signal Verification Engineer -Power Management ICs
What You’ll Do
- Develop and execute mixed-signal verification plans for high-current IVR designs.
- Build and maintain analog behavioral models (Verilog-A / SystemVerilog real-number modeling) for power stages, integrated inductors, PDN, and analog blocks.
- Perform analog-digital co-simulation using industry-standard tools (Cadence Xcelium + Spectre, Synopsys VCS + FineSim / CustomSim, or AMS Designer).
- Verify digital control loops.
- Create testbenches for key performance metrics: transient response (load steps), loop stability, efficiency, ripple, over-current / over-voltage protection, and startup/shutdown sequences.
- Run regressions across PVT corners, Monte-Carlo analysis, and corner-case scenarios.
- Debug mixed-signal issues at both transistor-level and behavioral level.
- Collaborate closely with analog designers, digital designers, and system engineers to close verification coverage.
- Develop automated verification scripts and improve verification methodology for faster turnaround.
- Support post-silicon validation by correlating simulation results with lab measurements.
What We’re Looking For
- 5+ years of hands-on experience in mixed-signal verification of power management ICs or analog/mixed-signal SoCs.
- Strong proficiency in mixed-signal simulation flows: Real Number Modeling (RNM) and Verilog-A behavioral modeling.
- Solid understanding of power converter topologies (buck, multi-phase, 3-level buck, switched-capacitor converters).
- Good knowledge of digital control concepts for power converters (PID controllers, DPWM, digital feedback loops).
- Experience with MATLAB/Simulink for system-level modeling and testbench reference generation.
- Proficiency in SystemVerilog and UVM for digital/mixed-signal testbenches.
- Familiarity with Cadence Virtuoso, Spectre, or Synopsys CustomSim for analog simulation.
- Understanding of analog non-idealities (quantization effects, loop delay, sensor offsets, PDN resonances, inductor non-linearities).
- BSEE / MSEE with 8+ years relevant experience.
- Nice to Have: Experience verifying high-frequency IVRs, PoL regulators, or high-current power delivery systems; experience with SIMPLIS, PLECS, or Simulink for system-level power electronics validation; experience with digital PID controller verification and fixed-point arithmetic effects; exposure to advanced packaging and on-die inductor modeling; scripting skills in Python, Perl, or Tcl for automation.
About TylSemi, Inc.
TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale. This isn't a nice-to-have. It's the critical path.
The Opportunity
The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve.
Culture & Team
No Politics, No Bureaucracy
Move Fast, Ship Real Products
Ownership mindset.
Bias for action.
Deep technical expertise.
Low ego, high standards.
The Ask
If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We're asking you to walk away from that and bet on us. Here's Why You Should
The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI. This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk.