Senior Member of Technical Staff (CMP) Engineer

Core Responsibilities

• Technical Leadership Process Development & Optimization: Lead CMP process development from concept through HVM implementation across multiple advanced technology nodes
• Cross-Node Alignment: Drive standardization and best practices across Intel's technology portfolio to maximize efficiency and yield
• Problem Resolution: Own and resolve complex CMP-related yield and manufacturing issues using data-driven approaches and structured problem-solving methodologies
• Strategic Execution Customer-Centric Delivery: Align technical strategies with customer requirements and business objectives, ensuring on-time delivery of robust solutions
• Technology Transfer: Bridge technology development and manufacturing teams to ensure smooth transition of CMP processes to production
• Continuous Improvement: Drive ongoing optimization initiatives to enhance process capability, yield, and manufacturing efficiency

Collaboration & Leadership

• Cross-Functional Partnership: Work closely with Integration, Device, Yield, Factory, Quality, and Customer Engineering teams
• Supplier Engagement: Collaborate with equipment and consumables suppliers to co-develop and optimize CMP solutions
• Team Development: Mentor junior engineers and provide technical guidance across the organization

Qualifications

• The Minimum qualifications are required to be initially considered for this position.
• Master's degree in Chemical Engineering, Materials Science, Electrical Engineering, Mechanical Engineering, Physics, or related technical field
• 7+ years of experience in semiconductor manufacturing / process development or technology development
• 4+ years of direct experience in Chemical Mechanical Planarization (CMP) process development experience with hands-on process tuning and characterization
• Experience with major CMP equipment platforms in one of the following platforms (AMAT, Ebara, etc.)
• Experience with CMP consumables (e.g. slurries, pads, conditioning disks, filters, clean chemistries)
• Previous semiconductor foundry experience

Preferred Qualifications

• Doctorate in Chemical Engineering, Materials Science, Electrical Engineering, Mechanical Engineering, Physics, or related technical field
• Experience with advanced technology nodes (e.g. sub-10nm logic, specifically in Gate All Around (GAA) architectures with track record of successful technology development and HVM implementation)
• Previous semiconductor foundry experience
• Experience with advanced technology nodes (e.g. sub-10nm logic, specifically in Gate All Around (GAA) architectures with track record of successful technology development and HVM implementation)
• Experience with CMP integration with other process modules (e.g. deposition, lithography, etch, clean) and CMP-relevant metrology with understanding of CMP impact on device performance and yield
• Experience with CMP-relevant metrology and process control (e.g. thickness, topography, defects, roughness, particles)