Senior Manager, ASIC Design

About the Role

We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals. This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.

Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology delivering a tenfold increase in performance and energy efficiency. The technology is available as optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB), enabling high bandwidth, low power, and low latency optical interfaces for AI accelerators and GPUs. It supports tens of terabits per second bandwidth with nanosecond latencies, optimizing XPUs for training and inference while reducing TCO2 impact.

Responsibilities

• Lead and manage a team in the end-to-end design and development of high-performance ASICs.
• Ensure technical excellence, on-time project delivery, and alignment with company goals.
• Oversee microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Optimize designs for PPA (power, performance, area) and integrate major subsystems (interconnect, I/O, memory).
• Coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
• Collaborate with cross-functional teams and stakeholders to drive successful product delivery.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 5-10 years of related professional experience, or a Master’s degree and/or PhD with 3-5 years of experience, or equivalent professional experience.
• 8+ years of ASIC/SOC digital design experience.
• 3+ years of people management experience.
• Strong knowledge across the full ASIC/SOC development cycle from microarchitecture to tape-out in advanced process technologies.
• Hands-on design experience with industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink, etc.
• Proficiency with front-end development tools/methodologies and scripting for automation and flow integration.

Skills

• Excellent leadership, communication, team building, and stakeholder management skills.
• Ability to work under tight schedules and manage multiple projects simultaneously.
• Demonstrated ability to optimize designs for PPA (power, performance, area).

Pay

Expected base pay range: $161,600 - $239,210 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.