Senior LPU ASIC Engineer

About the role

The Senior LPU ASIC Engineer will play a crucial role in our innovative LPU chip design. They will be responsible for full-flow ownership from synthesis to tapeout, cross-functional optimization, methodology innovation, and tapeout execution.

Responsibilities

• Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level.
• Cross-Functional Optimization: Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation.
• Tapeout Execution: Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.
• Methodology Innovation: Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.

Requirements

• B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred)
• 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes
• Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification
• Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures
• Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints
• Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle
• Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure
• Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations
• EDA Tool Proficiency: Expert-level command of industry-standard tool suites for end-to-end physical design flows
• Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency
• Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces (a plus)

Qualifications

• B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred)
• 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes
• Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification
• Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures
• Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints
• Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle
• Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure
• Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations
• EDA Tool Proficiency: Expert-level command of industry-standard tool suites for end-to-end physical design flows
• Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency
• Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces (a plus)

Skills

• Full-Flow Ownership
• Low-Power Expertise
• Clock & Timing Mastery
• PPA Optimization
• Sign-off & Integrity
• DFT & Block-Level Integration
• EDA Tool Proficiency
• Automation & Innovation
• High-Speed IP Integration

Benefits

• Comprehensive benefits package
• Competitive base salary ranging from $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4
• Equity options
• See what we can offer to you and your family at www.nvidiabenefits.com/

Pay

Base salary range: $136,000 - $218,500 for Level 3, and $168,000 - $264,500 for Level 4.

Schedule

NVIDIA offers flexible scheduling options to support a healthy work-life balance.