Senior Logic Design Engineer, Cache Coherent Interconnects

About the role

This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence!

Responsibilities

• Writing readable high performance and low power RTL
• Synthesis and Timing closure
• Design documentation
• Collaborate with our verification team to verify the correctness of your unit
• Work with implementation to achieve your timing, area, performance and power goals
• Assist with timing closure of super units

Requirements

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience
• 5+ years of experience in processor or other related high performance semiconductor designs
• Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
• Strong communication and interpersonal skills are required along with the work in a dynamic, global team

Qualifications

• Your successful track record of mentoring junior engineers and interns a huge plus
• A strong background in computer architecture, cache coherency or high speed interconnects is helpful

Skills

• Computer Architecture
• Cache Coherency
• High Speed Interconnects

Benefits

• NVIDIA is widely considered to be one of the technology world’s most desirable employers.
• We have some of the most brilliant and hardworking people in the world working for us.

Pay

• Base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

Schedule

• Not specified