Micro-architect/Logic Designer, Coherent Interconnect

Position Summary

Samsung, a world leader in advanced semiconductor technology, is seeking a Micro-Architect/Logic Designer to lead the development of custom coherent interconnect IP and last level cache blocks. This role involves working closely with system architects, verification, performance/power, and design implementation teams. Responsibilities include owning and driving the RTL design, performance, and power optimization, as well as logic debug and timing closure.

Role And Responsibilities

• Drive the timely development of custom coherent interconnect IP and/or last level cache blocks.
• Partner with architects to help define next-generation Samsung coherent interconnects and LLC.
• Lead microarchitecture development and specification, from early high-level architectural exploration through microarchitectural research and arriving at a detailed specification.
• Collaborate with verification to verify the functionality and correctness of the design.
• Work with implementation to achieve timing and area goals.
• Produce quality RTL on schedule meeting PPA goals.
• Engage with performance and power team on achieving performance and power goals.
• Collaborate with physical design and CAD team to resolve implementation level details.
• Help mentor junior engineers in the team.

Skills And Qualifications

• 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years with a Master’s degree, or 6+ years with a PhD.
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs.
• Demonstrated successful architectural through RTL design experience on high performance digital designs.
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols.
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Preferred Candidates

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of coherent interconnect, memory controller, and/or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.

Our Team

The System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Total Rewards

• Base pay range: $151,000 - $251,800.
• MBO bonus compensation.
• Relocation eligibility.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Trade Secrets

By submitting an application, you agree not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.