Senior FPGA / RTL Design Engineer - Signal Processing

About the Company

Motorola Solutions is a global community united by the mission to help keep people safer everywhere. We build and connect technologies to protect people, property, and places, fostering collaboration critical for safer communities, schools, hospitals, businesses, and nations. Silvus Technologies, a wholly owned subsidiary of Motorola Solutions, is a leading provider of advanced MANET and MIMO communications systems. With deep roots in DARPA research, Silvus develops world-class communications technologies for defense, law enforcement, and public safety agencies worldwide, enabling secure and reliable connectivity in the toughest operational environments.

About the Role

Silvus is seeking a Senior FPGA Design Engineer—Signal Processing to join a talented team focused on the prime directive of “Keeping Our Heroes Connected.” In this role, you will participate in all aspects of the research and development process, from concept to field deployment, implementing novel signal processing algorithms for Silvus' MIMO wireless networking products. You will also support and develop FPGA-based designs for advanced wireless systems R&D, addressing challenging real-world communication needs.

This position is based at Silvus Technologies’ headquarters in West Los Angeles, CA, on a hybrid schedule with a minimum of 3 days onsite per week (Mondays, Wednesdays, and Thursdays).

Responsibilities

• Digital design architecting for wireless communication projects.
• Fixed-point design of signal processing blocks in collaboration with systems engineers.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting, including familiarity with logic analyzers.
• Provide support to the RF and Software Engineering teams.
• Perform other related duties as assigned.

Requirements

• Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
• Minimum 6 years of demonstrated experience in FPGA design; OR 4 years of FPGA design experience with a Master of Science degree; OR 2 years of FPGA design experience with a PhD degree.
• Demonstrated experience with fixed-point binary arithmetic and digital signal processing designs.
• Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Must be a U.S. Person (U.S. Citizen or Permanent Resident) due to clients under U.S. federal contracts.
• All employment is contingent upon the successful clearance of a background check and drug test.

Preferred Qualifications

• Master of Science degree in Electrical Engineering (MSEE).
• Experience using MATLAB.
• Experience with communication systems on FPGA or ASIC designs.

Working Conditions

• Primarily an office environment.
• Occasional exposure to heat, cold, and allergens during field tests or demonstrations.
• Physical requirements include:
  • Lifting equipment up to 20 lbs. for demonstrations and testing.
  • Bending, reaching, kneeling, or squatting to access shelves or equipment.
  • Walking and moving within labs.

Pay

$125,000 - $195,000 annually. The pay range is based on market research and peer data and will vary depending on the candidate’s experience and qualifications.

Schedule

Hybrid schedule with a minimum of 3 days onsite per week (Mondays, Wednesdays, and Thursdays).

Benefits

• Incentive Bonus Plans
• Medical, Dental, and Vision benefits
• 401K with Company Match
• 10 Paid Holidays
• Generous Paid Time Off Packages
• Employee Stock Purchase Plan
• Paid Parental & Family Leave
• Domestic relocation assistance provided

Additional Information

• Travel requirements: Under 10%.
• Referral Payment Plan available.