Senior FPGA Signal Processing Engineer

Location: Fairfax, VA | Reports to: Senior Manager, FPGA Engineering | Supervises: No

About the role

The Senior FPGA Signal Processing Engineer (Image/Video and Compression) will design and develop advanced FPGA‑based imaging and data‑compression solutions for space‑based electronic systems. The role involves architecting, implementing, and verifying high‑speed programmable‑logic designs that process, analyze, and compress image and video data, translating existing algorithms into efficient FPGA implementations, and collaborating across hardware, firmware, and software teams to deliver mission‑critical solutions for DoD, Intelligence Community, and civil space customers.

Responsibilities

• Work within a multi‑discipline team designing advanced processing, imaging, sensor, RF, networking, and data‑storage solutions for space applications, using the latest AMD (Xilinx) FPGA technologies such as Zynq UltraScale+ MPSoC, Zynq UltraScale+ RFSoC, and Versal ACAP.
• Architect FPGA‑based pipelines for image/video or other sensor data processing and compression, covering data acquisition, pre‑processing, transformation, compression, and output formatting.
• Analyze existing image/video processing and compression algorithms (often developed in MATLAB), understand their performance characteristics, and adapt or tune them for specific application constraints.
• Use MATLAB (and optionally Simulink) to evaluate and refine algorithms, establish golden reference models for output quality, rate/distortion behavior, and numerical accuracy, supporting their translation into hardware.
• Translate MATLAB‑level algorithms into FPGA architectures by partitioning functionality, performing fixed‑point analysis, quantization, and word‑length optimization, and mapping to DSP blocks, memory structures, and streaming data paths.
• Create and maintain complete FPGA designs using VHDL or Verilog, employing Vivado IP Integrator where applicable, with emphasis on efficient datapath architecture, deterministic latency, and high‑throughput implementations.
• Code, simulate, and verify a wide range of RTL modules, including DSP‑oriented processing blocks, compression/decompression modules, and control logic/interfaces to external peripherals and sensors.
• Develop comprehensive simulation testbenches (e.g., SystemVerilog) to verify functional correctness, compare FPGA results against MATLAB golden models, and achieve high code coverage and regression robustness.
• Develop and maintain IP‑core‑level and top‑level design documentation, interface control documents, and performance/quality reports.
• Participate in and lead code reviews and design reviews.
• Collaborate closely with hardware and software engineers throughout integration to ensure correct implementation, configuration, and system‑level control, including driver/API definition where needed.
• Support system verification in an electronic lab environment, including data capture, performance evaluation, and system‑level debug using FPGA ILA‑based tools (Vivado HW Debugger, Chipscope, SmartDebug).
• Provide technical leadership on imaging and compression architectures across multiple programs, influencing technology roadmaps, IP reuse strategies, and standard algorithmic approaches.
• Mentor junior and mid‑level engineers.
• Perform other duties as assigned.

Required qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related technical field.
• Minimum of 6 years of related experience with a bachelor’s degree, or 4 years with a master’s degree.
• Experience implementing signal‑processing algorithms (preferably image/video processing or data compression) in FPGA hardware, including fixed‑point conversion, resource and throughput optimization, and validation against algorithmic models.
• Ability to understand, analyze, and adapt existing algorithms for specific applications and constraints.
• Proficiency in RTL logic design and coding using VHDL or Verilog.
• Experience with MATLAB or similar algorithmic modeling tools.
• Highly productive, self‑motivated, and able to contribute individually and within a distributed team.

Preferred qualifications

• Experience designing with Xilinx (AMD) FPGAs using Vivado or ISE.
• Experience designing with Microsemi (Microchip) FPGAs using Libero.
• Familiarity with logic simulation tools such as ModelSim, QuestaSim, and/or Aldec.
• Experience with lab test equipment such as logic analyzers, oscilloscopes, signal generators, and spectrum analyzers.
• Experience using revision control systems, such as Git.
• Proficiency in Linux and C/C++ development.

Pay

Full‑time salary range: $97,000 – $180,000. Actual compensation will be determined based on factors including relevant experience, skills, education, certifications, internal equity, business considerations, and geographic location.

Benefits

• Health, medical, dental, and vision insurance
• Basic life insurance with AD&D
• Short‑term and long‑term disability coverage
• Ancillary voluntary benefits (life with AD&D, accident, critical illness, hospital, pet)
• Spending accounts (HSA, FSA, DCFSA)
• Paid time off and holidays
• 401(k) with company match
• Tuition reimbursement
• Parental, maternity, and military leaves
• Annual discretionary bonus (for eligible roles)