Senior Engineer, RTL Design

Advancing the World’s Technology Together. Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves.

About the role

The Memory Solutions Lab (MSL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, and SRAM memory. MSL’s vision is to solve key problems and optimize architecture solutions for Cloud & Data center environments. We are an integral part of Samsung’s strong R&D focus & lab innovation engine, working closely with development teams to bring feature innovation to product roadmaps.

Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy.

Responsibilities

• Microarchitecture, RTL design, and verification.
• Develop new RTL IP for high performance Proofs of Concept (PoCs).
• Lab bring-up, lab test, and validation of RTL IPs.
• Research next generation memory and storage controller features.
• Research emerging technology standards.
• Work with hardware/software architects developing one-of-a-kind innovative FPGA prototypes and contribute to feasibility studies & developing solutions.
• Assist software architects developing Linux/Windows device drivers, test, and debug.
• Participate in value proposition studies, publish papers in leading journals and conferences, and file patents.
• Complete other responsibilities as assigned.

Requirements

• BS with 5 years of RTL Development, MS with 3 years of RTL Development, or Ph.D. in Computer Engineering or Electrical Engineering.
• Familiarity with FPGA design tool flows, synthesis, timing analysis, partitioning, FPGA programming, bring-up, and testing is a plus.
• In-depth background in HDL development, Verilog coding, integration, synthesis, debug, simulation, test bench creation, and debug using CAD tools (Synopsys, Mentor, Cadence tools).
• Hands-on experience with hardware board bring-up, server system integration, and software integration.
• Experience and exposure to PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet protocols.
• Must be highly motivated with excellent verbal and written communication skills.
• Demonstrated attention to detail.
• Ability to meet aggressive project deadlines in a team environment.
• Ability to work successfully with cross-functional teams, including coordinating across organizational boundaries and geographies.

Skills

• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support, and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Benefits

• Give Back: Charitable giving match and frequent opportunities to get involved in supporting the community.
• Enjoy Time Away: 4+ weeks of paid time off a year, plus holidays and sick leave.
• Care for Family: Stipend for fertility care or adoption, medical travel support, and virtual vet care for pets.
• Prioritize Emotional Wellness: On-demand apps and free confidential therapy sessions.
• Stay Fit: Onsite Café and gym, plus virtual fitness classes.
• Embrace Flexibility: A flexible environment to help you find the right work-life balance.
• Incentive opportunities that reward employees based on individual and company performance.
• Comprehensive benefits including Medical, Dental, Vision, and 401k.

Pay

Base Pay Range: $138,000—$206,000 USD